SM320LF2407-EP Datasheet, PDF (76/112 Pages) Texas Instruments – 
DSP CONTROLLERS

SM320LF2407AĆEP
DSP CONTROLLERS
SGUS036B − JULY 2003 − REVISED OCTOBER 2003
PARAMETER MEASUREMENT INFORMATION
SPICLK
(clock polarity = 0)
SPICLK
(clock polarity = 1)
1
2
3
4
5
SPISIMO
Master Out Data Is Valid
SPISOMI
8
9
Master In Data
Must Be Valid
SPISTE†
† _{The SPISTE signal must be active before the SPI communication stream starts; the SPISTE signal must remain active}
until the SPI communication stream is complete.
Figure 34. SPI Master Mode External Timing (Clock Phase = 0)
76
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