SM320LF2407-EP Datasheet, PDF (73/112 Pages) Texas Instruments – 
DSP CONTROLLERS

SM320LF2407AĆEP
DSP CONTROLLERS
interrupt timings
INT refers to XINT1 and XINT2. PDP refers to PDPINTx.
SGUS036B − JULY 2003 − REVISED OCTOBER 2003
switching characteristics over recommended operating conditions (see Figure 31)
PARAMETER
td(PDP-PWM)HZ Delay time, PDPINTx low to PWM high-impedance state
td(INT)
Delay time, INT low/high to interrupt-vector fetch
† _{Not verified; for informational purposes only.}
MIN
10tc(CO)
MAX
12†
UNIT
ns
ns
timing requirements (see Figure 31)
tw(INT)‡
Pulse duration, INT input low/high
tw(PDP)‡
Pulse duration, PDPINTx input low
‡ _{This is different from 240x devices.}
if bit 6 of SCSR2 = 0
if bit 6 of SCSR2 = 1
if bit 6 of SCSR2 = 0
if bit 6 of SCSR2 = 1
MIN
6tc(CO)
12tc(CO)
6tc(CO)
12tc(CO)
MAX
UNIT
ns
ns
CLKOUT
PDPINTx
PWM†
tw(PDP)
td(PDP-PWM)HZ
XINT1, XINT2
A0−A15
tw(INT)
td(INT)
Interrupt Vector
† _{PWM refers to all the PWM pins in the device (i.e., PWMn and TnPWM pins). The state of the PWM pins after PDPINTx is taken}
high depends on the state of the FCOMPOE bit.
Figure 31. External Interrupts Timing
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