SM320LF2407-EP Datasheet, PDF (21/112 Pages) Texas Instruments – 
DSP CONTROLLERS

SM320LF2407AĆEP
DSP CONTROLLERS
functional block diagram of the 2407A DSP CPU
SGUS036B − JULY 2003 − REVISED OCTOBER 2003
Program Bus
IS
DS
PS
R/W
STRB
READY
XF
XTAL1
CLKOUT
XTAL2
MUX
NPAR
A15−A0
D15−D0
RS
MP/MC
XINT[1−2]
2
16
16
PC
RD
WE
PAR MSTACK
MUX
Stack 8 × 16
FLASH EEPROM/
ROM
16
16
16
Program Control
(PCTRL)
16
16
16
16
3
ARP(3)
3
3
ARB(3)
3
16
16
16
AR0(16)
AR1(16)
AR2(16)
AR3(16)
AR4(16)
AR5(16)
AR6(16)
AR7(16)
9
DP(9)
9
16
16 _{Memory Map}
Register
IMR (16)
IFR (16)
GREG (16)
16
ARAU(16)
MUX
MUX
Data/Prog
DARAM
B0 (256 × 16)
MUX
16
MUX
Data
DARAM
B2 (32 × 16)
B1 (256 × 16)
16
Data Bus
16
7
16
LSB
from
IR
16
MUX
16 16
MUX
16
TREG0(16)
Multiplier
ISCALE (0−16)
PREG(32)
32
PSCALE (−6,ā 0,ā 1,ā 4)
32
32
MUX
32
CALU(32)
32
32
C ACCH(16) ACCL(16)
32
OSCALE (0−7)
16
16
NOTES: A. See Table 4 for symbol descriptions.
B. For clarity, the data and program buses are shown as single buses although they include address and data bits.
C. Refer to the TMS320F/C24x DSP Controllers Reference Guide: CPU and Instruction Set (literature number SPRU160) for CPU
instruction set information.
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
21