SM320LF2407-EP Datasheet, PDF (43/112 Pages) Texas Instruments – 
DSP CONTROLLERS

SM320LF2407AĆEP
DSP CONTROLLERS
SGUS036B − JULY 2003 − REVISED OCTOBER 2003
PLL-based clock module
The 240xA has an on-chip, PLL-based clock module. This module provides all the necessary clocking signals
for the device, as well as control for low-power mode entry. The PLL has a 3-bit ratio control to select different
CPU clock rates. See Figure 9 for the PLL Clock Module Block Diagram, Table 9 for clock rates, and Table 10
for the loop filter component values.
The PLL-based clock module provides two modes of operation:
D Crystal-operation
This mode allows the use of an external crystal/resonator to provide the time base to the device.
D External clock source operation
This mode allows the internal oscillator to be bypassed. The device clocks are generated from an external
clock source input on the XTAL1/CLKIN pin. In this case, an external oscillator clock is connected to the
XTAL1/CLKIN pin.
RESONATOR/
CRYSTAL
XTAL1/CLKIN
Cb1
XTAL2
Cb2
Fin
PLL
CLKOUT
PLLF
C2
R1
XTAL
OSC
C1
PLLF2
3-bit
PLL Select
(SCSR1.[11:9])
Figure 9. PLL Clock Module Block Diagram
Table 9. PLL Clock Selection Through Bits (11−9) in SCSR1 Register
CLK PS2 CLK PS1 CLK PS0
CLKOUT
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
4 × Fin
2 × Fin
1.33 × Fin
1 × Fin
0.8 × Fin
0.66 × Fin
0.57 × Fin
0.5 × Fin
Default multiplication factor after reset is (1,1,1), i.e., 0.5 × Fin.
CAUTION:
The bootloader sets the PLL to x2 or x4 option. If the bootloader is used, the value of CLKIN
used should not force CLKOUT to exceed the maximum rated device speed. See the “Boot
ROM” section for more details.
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
43