SM320LF2407-EP Datasheet, PDF (92/112 Pages) Texas Instruments – 
DSP CONTROLLERS

SM320LF2407AĆEP
DSP CONTROLLERS
SGUS036B − JULY 2003 − REVISED OCTOBER 2003
10-bit analog-to-digital converter (ADC)
The 10-bit ADC has a separate power bus for its analog circuitry. These pins are referred to as V_CCA and V_SSA.
The power bus isolation is to enhance ADC performance by preventing digital switching noise of the logic
circuitry that can be present on V_SS and V_CC from coupling into the ADC analog stage. All ADC specifications
are given with respect to V_SSA unless otherwise noted.
Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-bit (1024 values)
Monotonic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Assured
Output conversion mode . . . . . . . . . . . . . . . . . . . 000h to 3FFh (000h for V_I ≤ V_REFLO; 3FFh for V_I ≥ V_REFHI)
Minimum conversion time (including sample time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 ns
recommended operating conditions
MIN
NOM
VCCA
Analog supply voltage
3.0
3.3
VSSA
VREFHI
VREFLO
Analog ground
Analog supply reference source†
Analog ground reference source†
0
VREFLO
VSSA
VAI
Analog input voltage, ADCIN00−ADCIN07
VREFLO
† _{VREFHI and VREFLO must be stable, within ±1/2 LSB of the required resolution, during the entire conversion time.}
MAX
3.6
VCCA
VREFHI
VREFHI
UNIT
V
V
V
V
V
ADC operating frequency (LF240xA)
ADC operating frequency
MIN MAX UNIT
4 30 MHz
operating characteristics over recommended operating condition ranges^†
PARAMETER
DESCRIPTION
MIN TYP MAX UNIT
ICCA
Analog supply current
VCCA = 3.3 V
VCCA = VREFHI = 3.3 V
PLL or OSC power
down
10
20 mA
1 mA
IADREFHI VREFHI input current
0.75 1.5 mA
IADCIN
Analog input leakage
1 mA
Cai
Analog input capacitance
Typical capacitive load on
analog input pin
Non-sampling
Sampling
10
pF
30
td(PU)
Delay time, power-up to ADC valid Time to stabilize analog stage after power-up
10 ms
Analog input source impedance needed for
ZAI
Analog input source impedance
conversions to remain within specifications at min
tw(SH)
53
10 Ω
Zero-offset error
"2
LSB
† _{Absolute resolution = 3.22 mV. At VREFHI = 3.3 V and VREFLO = 0 V, this is one LSB. As VREFHI decreases, VREFLO increases, or both, the LSB}
size decreases. Therefore, the absolute accuracy and differential/integral linearity errors in terms of LSBs increase.
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