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SM320LF2407-EP Datasheet, PDF (42/112 Pages) Texas Instruments – DSP CONTROLLERS | |||
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SM320LF2407AÄEP
DSP CONTROLLERS
SGUS036B â JULY 2003 â REVISED OCTOBER 2003
serial peripheral interface (SPI) module (continued)
Figure 8 is a block diagram of the SPI in slave mode.
SPIRXBUF.15 â0
SPIRXBUF
Buffer Register
Receiver
Overrun Flag
SPISTS.7
SPITXBUF.15 â0
16
SPITXBUF
Buffer Register
SPI INT FLAG
SPISTS.6
16
Overrun
INT ENA
SPICTL.4
SPI INT
ENA
SPICTL.0
To CPU
SPI Priority
SPIPRI.6
0 Level 1
INT
1 Level 5
INT
External
Connections
SPIDAT
Data Register
SPIDAT.15 â0
M
M
S
S
SW1
M
M
SPISIMO
Talk
SPICTL.1
S
S
SW2
SPISOMI
SPISTEâ
State Control
SPI Char SPICCR.3 â0
S
32 1 0
SPI Bit Rate
M
Internal
Clock
SPIBRR.6 â0
6543210
Master/Slave
SPICTL.2
SW3
Clock
S
Polarity
SPICCR.6
M
Clock
Phase
SPICTL.3
SPICLK
NOTE A: The diagram is shown in the slave mode.
â The SPISTE pin is driven low externally. Note that SW1, SW2, and SW3 are closed in this configuration. Refer to the following erratas for
restrictions on using the SPISTE pin:
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A DSP Controllers Silicon Errata
(literature number SPRZ002)
Figure 8. Four-Pin Serial Peripheral Interface Module Block Diagram
42
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