SM320LF2407-EP Datasheet, PDF (81/112 Pages) Texas Instruments – 
DSP CONTROLLERS

SM320LF2407AĆEP
DSP CONTROLLERS
SGUS036B − JULY 2003 − REVISED OCTOBER 2003
SPI slave mode external timing parameters (clock phase = 1)^†‡ (see Figure 37)
NO.
MIN
MAX
12 tc(SPC)S
Cycle time, SPICLK
13§ ^tw(SPCH)S
tw(SPCL)S
Pulse duration, SPICLK high (clock polarity = 0)
Pulse duration, SPICLK low (clock polarity = 1)
14§ ^tw(SPCL)S
tw(SPCH)S
Pulse duration, SPICLK low (clock polarity = 0)
Pulse duration, SPICLK high (clock polarity = 1)
17§ ^{tsu(SOMI-SPCH)S Setup time, SPISOMI before SPICLK high (clock polarity = 0)}
tsu(SOMI-SPCL)S Setup time, SPISOMI before SPICLK low (clock polarity = 1)
tv(SPCH-SOMI)S
18§
tv(SPCL-SOMI)S
Valid time, SPISOMI data valid after SPICLK high
(clock polarity =0)
Valid time, SPISOMI data valid after SPICLK low
(clock polarity =1)
8tc(CO)
0.5tc(SPC)S −10
0.5tc(SPC)S −10
0.5tc(SPC)S −10
0.5tc(SPC)S −10
0.125tc(SPC)S
0.125tc(SPC)S
0.5tc(SPC)S
0.5tc(SPC)S
0.5tc(SPC)S
0.5tc(SPC)S
0.75tc(SPC)S
0.75tc(SPC)S
21§
tsu(SIMO-SPCH)S
tsu(SIMO-SPCL)S
Setup time, SPISIMO before SPICLK high (clock polarity = 0)
Setup time, SPISIMO before SPICLK low (clock polarity = 1)
0
0
tv(SPCH-SIMO)S
22§
tv(SPCL-SIMO)S
Valid time, SPISIMO data valid after SPICLK high
(clock polarity = 0)
Valid time, SPISIMO data valid after SPICLK low
(clock polarity = 1)
0.5tc(SPC)S
0.5tc(SPC)S
† _{The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is set.}
‡ _{tc = system clock cycle time = 1/CLKOUT = tc(CO)}
§ _{The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).}
UNIT
ns
ns
ns
ns
ns
ns
ns
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