SM320LF2407-EP Datasheet, PDF (62/112 Pages) Texas Instruments – 
DSP CONTROLLERS

SM320LF2407AĆEP
DSP CONTROLLERS
SGUS036B − JULY 2003 − REVISED OCTOBER 2003
PARAMETER MEASUREMENT INFORMATION
Tester Pin
Electronics
VLOAD
IOL
50 Ω
CT
Output
Under
Test
IOH
Where:
signal transition levels
IOL
=
IOH
=
VLOAD =
CT
=
2 mA (all outputs)
300 µA (all outputs)
1.5 V
50-pF typical load-circuit capacitance
Figure 16. Test Load Circuit
The data in this section is shown for the 3.3-V version. Note that some of the signals use different reference
voltages, see the recommended operating conditions table. Output levels are driven to a minimum logic-high
level of 2.4 V and to a maximum logic-low level of 0.8 V.
Figure 17 shows output levels.
2.4 V (VOH)
80%
20%
0.4 V (VOL)
Figure 17. Output Levels
Output transition times are specified as follows:
D For a high-to-low transition, the level at which the output is said to be no longer high is below 80% of the
total voltage range and lower and the level at which the output is said to be low is 20% of the total voltage
range and lower.
D For a low-to-high transition, the level at which the output is said to be no longer low is 20% of the total voltage
range and higher and the level at which the output is said to be high is 80% of the total voltage range and
higher.
Figure 18 shows the input levels.
2.0 V (VIH)
90%
10%
0.8 V (VIL)
Figure 18. Input Levels
Input transition times are specified as follows:
D For a high-to-low transition on an input signal, the level at which the input is said to be no longer high is 90%
of the total voltage range and lower and the level at which the input is said to be low is 10% of the total voltage
range and lower.
D For a low-to-high transition on an input signal, the level at which the input is said to be no longer low is 10%
of the total voltage range and higher and the level at which the input is said to be high is 90% of the total
voltage range and higher.
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