SM320LF2407-EP Datasheet, PDF (82/112 Pages) Texas Instruments – 
DSP CONTROLLERS

SM320LF2407AĆEP
DSP CONTROLLERS
SGUS036B − JULY 2003 − REVISED OCTOBER 2003
PARAMETER MEASUREMENT INFORMATION
SPICLK
(clock polarity = 0)
SPICLK
(clock polarity = 1)
12
13
14
17
18
SPISOMI
SPISOMI Data Is Valid
SPISIMO
21
22
SPISIMO Data
Must Be Valid
Data Valid
SPISTE†
† _{The SPISTE signal must be active before the SPI communication stream starts; the SPISTE signal must remain active until}
the SPI communication stream is complete.
Figure 37. SPI Slave Mode External Timing (Clock Phase = 1)
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