SM320LF2407-EP Datasheet, PDF (64/112 Pages) Texas Instruments – 
DSP CONTROLLERS

SM320LF2407AĆEP
DSP CONTROLLERS
SGUS036B − JULY 2003 − REVISED OCTOBER 2003
external reference crystal/clock with PLL circuit enabled
timings with the PLL circuit enabled
PARAMETER
MIN MAX
Resonator
4
13
fx
Input clock frequency†
Crystal
4
20
CLKIN
4
20
† _{Input frequency should be adjusted (CLK PS bits in SCSR1 register) such that CLKOUT = 40 MHz maximum, 4 MHz minimum.}
UNIT
MHz
switching characteristics over recommended operating conditions [H = 0.5 t_c(CO)] (see Figure 19)
tc(CO)
PARAMETER
Cycle time, CLKOUT
PLL MODE
×4 mode†
MIN TYP
25
MAX UNIT
ns
tf(CO)
tr(CO)
tw(COL)
tw(COH)
Fall time, CLKOUT
Rise time, CLKOUT
Pulse duration, CLKOUT low
Pulse duration, CLKOUT high
4
4
H −3
H
H −3
H
ns
ns
H +3 ns
H +3 ns
tt
Transition time, PLL synchronized after RS pin high
4096tc(Cl) ns
† _{Input frequency should be adjusted (CLK PS bits in SCSR1 register) such that CLKOUT = 40 MHz maximum, 4 MHz minimum.}
timing requirements (see Figure 19)
tc(Cl)
tf(Cl)
tr(Cl)
tw(CIL)
tw(CIH)
Cycle time, XTAL1/CLKIN
Fall time, XTAL1/CLKIN
Rise time, XTAL1/CLKIN
Pulse duration, XTAL1/CLKIN low as a percentage of tc(Cl)
Pulse duration, XTAL1/CLKIN high as a percentage of tc(Cl)
MIN MAX UNIT
250 ns
5 ns
5 ns
40
60 %
40
60 %
XTAL1/CLKIN
CLKOUT
tw(CIH)
tw(COH)
tc(CO)
tc(CI)
tf(Cl)
tw(CIL)
tr(Cl)
tw(COL) tr(CO)
tf(CO)
Figure 19. CLKIN-to-CLKOUT Timing with PLL and External Clock in ×4 Mode
64
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443