SM320LF2407-EP Datasheet, PDF (38/112 Pages) Texas Instruments – 
DSP CONTROLLERS

SM320LF2407AĆEP
DSP CONTROLLERS
SGUS036B − JULY 2003 − REVISED OCTOBER 2003
controller area network (CAN) module (continued)
CAN controller architecture
Figure 6 shows the basic architecture of the CAN controller through this block diagram of the CAN Peripherals.
CAN Module
CPU
Control/Status Registers
Interrupt Logic
CPU Interface/
Memory Management Unit
Control Bus
Transmit Buffer
CAN
Core
CANTX
CAN
Transceiver
CANRX
R mailbox 0
R
mailbox 1
T/R
mailbox 2
T/R
mailbox 3
T
mailbox 4
T
mailbox 5
RAM 48x16
Temporary Receive Buffer
Data
ID
Control Logic
Matchid
Acceptance Filter
Figure 6. CAN Module Block Diagram
The mailboxes are situated in one 48-word x 16-bit RAM. It can be written to or read by the CPU or the CAN.
The CAN write or read access, as well as the CPU read access, needs one clock cycle. The CPU write access
needs two clock cycles. In these two clock cycles, the CAN performs a read-modify-write cycle and, therefore,
inserts one wait state for the CPU.
Address bit 0 of the address bus used when accessing the RAM decides if the lower (0) or the higher (1)
16-bit word of the 32-bit word is taken. The RAM location is determined by the upper bits 5 to 1 of the address
bus.
Table 8. 3.3-V CAN Transceivers for the 320Lx240xA DSPs
INTEGRATED
PART NUMBER
LOW-POWER MODE
SLOPE CON-
Vref PIN
TA
TROL
SN65HVD230QDRQ1 370 µA standby mode
Yes
Yes
SN65HVD231QDRQ1
40 nA sleep mode
Yes
Yes
−40°C to 125°C
SN65HVD232QDRQ1 No standby or sleep mode
No
No
† _{This is the nomenclature printed on the device, since the footprint is too small to accommodate the entire part number.}
MARKED AS†
230Q1
231Q1
232Q1
38
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