SM320LF2407-EP Datasheet, PDF (9/112 Pages) Texas Instruments – 
DSP CONTROLLERS

SM320LF2407AĆEP
DSP CONTROLLERS
SGUS036B − JULY 2003 − REVISED OCTOBER 2003
pin functions (continued)
Table 2. LF240xA and LC240xA Pin List and Package Options^†‡ (Continued)
PIN NAME
LF2407A
(144-PGE)
DESCRIPTION
EXTERNAL INTERRUPTS, CLOCK
Device reset. RS causes the 240xA to terminate execution and sets PC = 0. When RS is brought
RS
133
to a high level, execution begins at location zero of program memory. RS affects (or sets to zero)
various registers and status bits. When the watchdog timer overflows, it initiates a system reset
pulse that is reflected on the RS pin. The RS pin is an open drain with a pullup. (↑)
PDPINTA
Power drive protection interrupt input. This interrupt, when activated, puts the PWM output pins
7
(EVA) in the high-impedance state should motor drive/power converter abnormalities, such as
overvoltage or overcurrent, etc., arise. PDPINTA is a falling-edge-sensitive interrupt. (↑)
XINT1/IOPA2
23
External user interrupt 1 or GPIO. Both XINT1 and XINT2 are edge-sensitive. The edge polarity
is programmable. (↑)
XINT2/ADCSOC/IOPD0
External user interrupt 2 and ADC start of conversion or GPIO. External “start-of-conversion” input
21
for ADC/GPIO. Both XINT1 and XINT2 are edge-sensitive. The edge polarity is
programmable. (↑)
CLKOUT/IOPE0
Clock output or GPIO. This pin outputs either the CPU clock (CLKOUT) or the watchdog clock
73
(WDCLK). The selection is made by the CLKSRC bit (bit 14) of the system control and status
register (SCSR). This pin can be used as a GPIO if not used as a clock output pin. (↑)
PDPINTB
Power drive protection interrupt input. This interrupt, when activated, puts the PWM output pins
137
(EVB) in the high-impedance state should motor drive/power converter abnormalities, such as
overvoltage or overcurrent, etc., arise. PDPINTB is a falling-edge-sensitive interrupt. (↑)
OSCILLATOR, PLL, FLASH, BOOT, AND MISCELLANEOUS
XTAL1/CLKIN
123
PLL oscillator input pin. Crystal input to PLL/clock source input to PLL. XTAL1/CLKIN is tied to
one side of a reference crystal.
XTAL2
124
Crystal output. PLL oscillator output pin. XTAL2 is tied to one side of a reference crystal. This pin
goes in the high-impedance state when EMU1/OFF is active low.
PLLVCCA
IOPF6
12
PLL supply (3.3 V)
131
General-purpose I/O (↑)
BOOT_EN
121
Boot ROM enable, GPO, XF. This pin will be sampled as input (BOOT_EN) to update SCSR2.3
BOOT_EN /
(BOOT_EN bit) during reset and then driven as an output signal for XF. After reset, XF is driven
XF
high. ROM devices do not have boot ROM, hence, no BOOT_EN modes. The BOOT_EN pin must
XF
121
be driven with a passive circuit only. (↑)
PLLF
11
PLL loop filter input 1
PLLF2
10
PLL loop filter input 2
VCCP (5V)
Flash programming voltage pin. This pin must be connected to a 5-V supply for Flash
programming. The Flash cannot be programmed if this pin is connected to GND. When not
programming the Flash (i.e., during normal device operation), this pin can either be left connected
58
to the 5-V supply or it can be tied to GND. This pin must not be left floating at any time. Do not use
any current-limiting resistor in series with the 5-V supply on this pin. This pin is a “no connect” (NC)
on ROM parts (i.e., this pin is not connected to any circuitry internal to the device). Connecting this
pin to 5 V or leaving it open makes no difference on ROM parts.
TP1
60
Test pin 1. Do not connect.
TP2
63
Test pin 2. Do not connect.
† _{Bold, italicized pin names indicate pin function after reset.}
‡ _{GPIO − General-purpose input/output pin. All GPIOs come up as input after reset.}
§ _{It is highly recommended that VCCA be isolated from the digital supply voltage (and VSSA from digital ground) to maintain the specified accuracy}
and improve the noise immunity of the ADC.
¶ _{Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high}
# _{No power supply pin (VDD, VDDO, VSS, or VSSO) should be left unconnected. All power supply pins must be connected appropriately for proper}
device operation.
LEGEND: ↑ − Internal pullup ↓ − Internal pulldown (Typical active pullup/pulldown value is ±16 µA.)
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