SM320LF2407-EP Datasheet, PDF (40/112 Pages) Texas Instruments – 
DSP CONTROLLERS

SM320LF2407AĆEP
DSP CONTROLLERS
SGUS036B − JULY 2003 − REVISED OCTOBER 2003
serial communications interface (SCI) module (continued)
Figure 7 shows the SCI module block diagram.
Frame Format and Mode
Parity
Even/Odd Enable
SCICCR.6 SCICCR.5
TXWAKE
SCICTL1.3
1
WUT
SCITXBUF.7−0
Transmitter-Data
Buffer Register
8
TXSHF
Register
Internal
Clock
SCIHBAUD. 15 −8
Baud Rate
MSbyte
Register
SCILBAUD. 7 −0
Baud Rate
LSbyte
Register
SCI TX Interrupt
TXRDY
TX INT ENA
SCICTL2.7
TX EMPTY
SCICTL2.0
SCICTL2.6
TXINT
External
Connections
TXENA
SCICTL1.1
SCITXD
SCI Priority Level
1
Level 5 Int.
0
Level 1 Int.
SCI TX
Priority
SCIPRI.6
Level 5 Int. ¹
Level 1 Int. ⁰
SCI RX
Priority
SCIPRI.5
SCITXD
RXWAKE
SCIRXST.1
RX ERR INT ENA
SCICTL1.6
RX Error
SCIRXST.7 SCIRXST.4 −2
RX Error
FE OE PE
RXSHF
Register
SCIRXD
SCICTL1.0
RXENA
8
Receiver-Data
Buffer
Register
SCIRXBUF.7−0
SCI RX Interrupt
RXRDY RX/BK INT ENA
SCIRXST.6
BRKDT
SCIRXST.5
SCICTL2.1
SCIRXD
Figure 7. Serial Communications Interface (SCI) Module Block Diagram
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