SM320LF2407-EP Datasheet, PDF (108/112 Pages) Texas Instruments – 
DSP CONTROLLERS

SM320LF2407AĆEP
DSP CONTROLLERS
SGUS036B − JULY 2003 − REVISED OCTOBER 2003
peripheral register description (continued)
Table 18. LF240xA DSP Peripheral Register Description (Continued)
ADDR
BIT 15
BIT 7
077F0h
077F1h
077F2h
077F3h
0xx00h
0xx01h
—
—
—
PRECND
Mode0
0xx02h
BIT 14
BIT 6
—
—
—
ENG/R
Mode2
BIT 13
BIT 12
BIT 11
BIT 10
BIT 5
BIT 4
BIT 3
BIT 2
KEY REGISTERS
High Word of the 64-Bit KEY Register
Third Word of the 64-Bit KEY Register
Second Word of the 64-Bit KEY Register
Low Word of the 64-Bit KEY Register
PROGRAM MEMORY SPACE − FLASH REGISTERS
—
—
—
—
—
—
PWR DWN
KEY1
—
—
—
—
ENG/R
Mode1
ENG/R
Mode0
FCM3
FCM2
BIT 9
BIT 1
—
KEY0
WSVER EN
FCM1
BIT 8
BIT 0
REG
KEY3
KEY2
KEY1
KEY0
—
EXEC
PRECND
Mode1
FCM0
PMPC
CTRL^†
WADDR
0xx03h
—
0xx04h
—
—
0xx05h
—
—
0xx06h
—
—
0FF0Fh
—
0FFFFh
—
ISWS.1
—
—
—
—
—
—
—
—
—
ISWS.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SECT 4
SECT 3
—
—
ENABLE
ENABLE
I/O MEMORY SPACE
—
—
—
—
—
—
—
—
WAIT-STATE GENERATOR CONTROL REGISTER
—
—
—
BVIS.1
DSWS.2
DSWS.1
DSWS.0
PSWS.2
Indicates change with respect to the F243/F241, C242 device register maps.
† _{Register shown with bits set in register mode.}
—
—
—
—
—
SECT 2
ENABLE
—
—
BVIS.0
PSWS.1
—
—
—
—
—
SECT 1
ENABLE
WDATA
TCR
ENAB
SECT
—
FCMR
—
ISWS.2
PSWS.0
WSGR
108
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