SM320LF2407-EP Datasheet, PDF (5/112 Pages) Texas Instruments – 
DSP CONTROLLERS

SM320LF2407AĆEP
DSP CONTROLLERS
functional block diagram of the 2407A DSP controller
SGUS036B − JULY 2003 − REVISED OCTOBER 2003
PLLF
XINT1/IOPA2
RS
DARAM (B0)
256 Words
PLL Clock
PLLVCCA
PLLF2
XTAL1/CLKIN
CLKOUT/IOPE0
XTAL2
TMS2
ADCIN00−ADCIN07
BIO/IOPC1
C2xx
DARAM (B1)
ADCIN08−ADCIN15
MP/MC
BOOT_EN/XF
VDD (3.3 V)
DSP
Core
256 Words
10-Bit ADC
(With Twin
Autosequencer)
VCCA
VSSA
VREFHI
VSS
DARAM (B2)
VREFLO
32 Words
ÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈ _{SARAM (2K Words)}
ÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈ _TP1
TP2
ÈÈÈÈÈÈÈÈÈÈÈÈÈÈ _VCCP(5V)
ÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈ _A0−A15
D0−D15
ÈÈÈÈÈÈÈÈ _{PS, DS, IS}
ÈÈÈÈÈÈÈÈ _R/W
RD
ÈÈÈÈÈÈÈÈ _READY
ÈÈÈÈÈÈÈÈ _STRB
WE
ÈÈÈÈÈÈÈÈ _{ENA_144}
ÈÈÈÈÈÈÈÈ _{VIS_OE}
ÈÈÈÈÈÈÈÈ _{W/R / IOPC0}
PDPINTA
ÈÈÈÈÈÈÈÈÈÈÈÈÈÈ _{CAP1/QEP1/IOPA3}
ÈÈÈÈÈÈÈ _{CAP2/QEP2/IOPA4}
CAP3/IOPA5
ÈÈÈÈÈÈÈ _PWM1/IOPA6
ÈÈÈÈÈÈÈ PWM2/IOPA7
PWM3/IOPB0
ÈÈÈÈÈÈÈ _PWM4/IOPB1
ÈÈÈÈÈÈÈ PWM5/IOPB2
PWM6/IOPB3
ÈÈÈÈÈÈÈ _{T1PWM/T1CMP/IOPB4}
T2PWM/T2CMP/IOPB5
ÈÈÈÈÈÈÈ _TDIRA/IOPB6
ÈÈÈÈÈÈÈ _{TCLKINA/IOPB7}
Flash/ROM
(32K Words:
4K/12K/12K/4K)
External Memory
Interface
Event Manager A
D 3 × Capture Input
D 6 × Compare/PWM
Output
D 2 × GP
Timers/PWM
SCI
SPI
CAN
WD
Digital I/O
(Shared With
Other Pins)
JTAG Port
Event Manager B
D 3 × Capture Input
D 6 × Compare/PWM
Output
D 2 × GP
Timers/PWM
XINT2/ADCSOC/IOPD0
SCITXD/IOPA0
SCIRXD/IOPA1
SPISIMO/IOPC2
SPISOMI/IOPC3
SPICLK/IOPC4
SPISTE/IOPC5
CANTX/IOPC6
CANRX/IOPC7
Port A(0−7) IOPA[0:7]
Port B(0−7) IOPB[0:7]
Port C(0−7) IOPC[0:7]
Port D(0) IOPD[0]
Port E(0−7) IOPE[0:7]
Port F(0−6) IOPF[0:6]
TRST
TDO
TDI
TMS
TCK
EMU0
EMU1
PDPINTB
CAP4/QEP3/IOPE7
CAP5/QEP4/IOPF0
CAP6/IOPF1
PWM7/IOPE1
PWM8/IOPE2
PWM9/IOPE3
PWM10/IOPE4
PWM11/IOPE5
PWM12/IOPE6
T3PWM/T3CMP/IOPF2
T4PWM/T4CMP/IOPF3
TDIRB/IOPF4
TCLKINB/IOPF5
ÈÈÈÈÈÈÈ _{Indicates optional modules.}
ÈÈÈ _{The memory size and peripheral selection of these modules change for different 240xA devices.}
ÈÈÈÈÈÈ _{See Table 1 for device-specific details.}
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