SM320LF2407-EP Datasheet, PDF (39/112 Pages) Texas Instruments – 
DSP CONTROLLERS

SM320LF2407AĆEP
DSP CONTROLLERS
SGUS036B − JULY 2003 − REVISED OCTOBER 2003
CAN interrupt logic
There are two interrupt requests from the CAN module to the peripheral interrupt expansion (PIE) controller:
the mailbox interrupt and the error interrupt. Both interrupts can assert either a high-priority request or a
low-priority request to the CPU. Since CAN mailboxes can generate multiple interrupts, the software should
read the CAN_IFR register for every interrupt and prioritize the interrupt service, or else, these multiple
interrupts will not be recognized by the CPU and PIE hardware logic. Each interrupt routine should service all
the interrupt bits that are set and clear them after service.
serial communications interface (SCI) module
The 240xA devices include a serial communications interface (SCI) module. The SCI module supports digital
communications between the CPU and other asynchronous peripherals that use the standard
non-return-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own
separate enable and interrupt bits. Both can be operated independently or simultaneously in the full-duplex
mode. To ensure data integrity, the SCI checks received data for break detection, parity, overrun, and framing
errors. The bit rate is programmable to over 65 000 different speeds through a 16-bit baud-select register.
Features of the SCI module include:
D Two external pins:
− SCITXD: SCI transmit-output pin
− SCIRXD: SCI receive-input pin
NOTE: Both pins can be used as GPIO if not used for SCI.
D Baud rate programmable to 64K different rates
− Up to 2500 Kbps at 40-MHz CPUCLK
D Data-word format
− One start bit
− Data-word length programmable from one to eight bits
− Optional even/odd/no parity bit
− One or two stop bits
D Four error-detection flags: parity, overrun, framing, and break detection
D Two wake-up multiprocessor modes: idle-line and address bit
D Half- or full-duplex operation
D Double-buffered receive and transmit functions
D Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with
status flags.
− Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and
TX EMPTY flag (transmitter-shift register is empty)
− Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag
(break condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
D Separate enable bits for transmitter and receiver interrupts (except BRKDT)
D NRZ (non-return-to-zero) format
D Ten SCI module control registers located in the control register frame beginning at address 7050h
NOTE: All registers in this module are 8-bit registers that are connected to the 16-bit peripheral bus. When a register is accessed, the
register data is in the lower byte (7 −0), and the upper byte (15 −8) is read as zeros. Writing to the upper byte has no effect.
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