SM320LF2407-EP Datasheet, PDF (25/112 Pages) Texas Instruments – 
DSP CONTROLLERS

SM320LF2407AĆEP
DSP CONTROLLERS
SGUS036B − JULY 2003 − REVISED OCTOBER 2003
multiplier
The x240xA devices use a 16 x 16-bit hardware multiplier that is capable of computing a signed or an unsigned
32-bit product in a single machine cycle. All multiply instructions, except the MPYU (multiply unsigned)
instruction, perform a signed multiply operation. That is, two numbers being multiplied are treated as
2s-complement numbers, and the result is a 32-bit 2s-complement number. There are two registers associated
with the multiplier, as follow:
D 16-bit temporary register (TREG) that holds one of the operands for the multiplier
D 32-bit product register (PREG) that holds the product
Four product-shift modes (PM) are available at the PREG output (PSCALE). These shift modes are useful for
performing multiply/accumulate operations, performing fractional arithmetic, or justifying fractional products.
The PM field of status register ST1 specifies the PM shift mode, as shown in Table 6.
Table 6. PSCALE Product-Shift Modes
PM
SHIFT
DESCRIPTION
00
No shift Product feed to CALU or data bus with no shift
01
Left 1
Removes the extra sign bit generated in a 2s-complement multiply to produce a Q31 product
10
Left 4
Removes the extra 4 sign bits generated in a 16x13 2s-complement multiply to a produce a Q31 product when
using the multiply-by-a-13-bit constant
11
Right 6
Scales the product to allow up to 128 product accumulation without the possibility of accumulator overflow
The product can be shifted one bit to compensate for the extra sign bit gained in multiplying two 16-bit
2s-complement numbers (MPY instruction). A four-bit shift is used in conjunction with the MPY instruction with
a short immediate value (13 bits or less) to eliminate the four extra sign bits gained in multiplying a 16-bit number
by a 13-bit number. Finally, the output of PREG can be right-shifted 6 bits to enable the execution of up to
128 consecutive multiply/accumulates without the possibility of overflow.
The LT (load TREG) instruction normally loads TREG to provide one operand (from the data bus), and the MPY
(multiply) instruction provides the second operand (also from the data bus). A multiplication also can be
performed with a 13-bit immediate operand when using the MPY instruction. Then, a product is obtained every
two cycles. When the code is executing multiple multiplies and product sums, the CPU supports the pipelining
of the TREG load operations with CALU operations using the previous product. The pipeline operations that
run in parallel with loading the TREG include: load ACC with PREG (LTP); add PREG to ACC (LTA); add PREG
to ACC and shift TREG input data (DMOV) to next address in data memory (LTD); and subtract PREG from ACC
(LTS).
Two multiply/accumulate instructions (MAC and MACD) fully utilize the computational bandwidth of the
multiplier, allowing both operands to be processed simultaneously. The data for these operations can be
transferred to the multiplier each cycle by way of the program and data buses. This facilitates single-cycle
multiply/accumulates when used with the repeat (RPT) instruction. In these instructions, the coefficient
addresses are generated by program address generation (PAGEN) logic, while the data addresses are
generated by data address generation (DAGEN) logic. This allows the repeated instruction to access the values
from the coefficient table sequentially and step through the data in any of the indirect addressing modes.
The MACD instruction, when repeated, supports filter constructs (weighted running averages) so that as the
sum-of-products is executed, the sample data is shifted in memory to make room for the next sample and to
throw away the oldest sample.
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