SM320LF2407-EP Datasheet, PDF (83/112 Pages) Texas Instruments – 
DSP CONTROLLERS

external memory interface read timings
SM320LF2407AĆEP
DSP CONTROLLERS
SGUS036B − JULY 2003 − REVISED OCTOBER 2003
switching characteristics over recommended operating conditions for an external memory
interface read at 40 MHz [H = 0.5t_c(CO)] (see Figure 38)
PARAMETER
MIN MAX UNIT
td(COL-CNTL) Delay time, CLKOUT low to control valid
4 ns
td(COL-CNTH) Delay time, CLKOUT low to control inactive
5 ns
td(COL-A)RD Delay time, CLKOUT low to address valid
8 ns
td(COH-RDL) Delay time, CLKOUT high to RD strobe active
5 ns
td(COL-RDH) Delay time, CLKOUT low to RD strobe inactive high
−8
1 ns
td(COL-SL)
Delay time, CLKOUT low to STRB strobe active low
5 ns
td(COL-SH)
Delay time, CLKOUT low to STRB strobe inactive high
6 ns
td(WRN)
Delay time, W/R going low to R/W rising
5 ns
th(A)COL
Hold time, address valid after CLKOUT low
−1
ns
tsu(A)RD
Setup time, address valid before RD strobe active low
H−7
ns
th(A)RD
Hold time, address valid after RD strobe inactive high
0
ns
timing requirements [H = 0.5t_c(CO)] (see Figure 38)
ta(A)
Access time, read data from address valid
ta(RD)
Access time, read data from RD low
tsu(D)RD
Setup time, read data before RD strobe inactive high
th(D)RD
Hold time, read data after RD strobe inactive high
th(AIV-D)
Hold time, read data after address invalid
† _{Not verified; for informational purposes only.}
MIN MAX
2H −10
H−7
8
0†
0†
UNIT
ns
ns
ns
ns
ns
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