SM320LF2407-EP Datasheet, PDF (35/112 Pages) Texas Instruments – 
DSP CONTROLLERS

SM320LF2407AĆEP
DSP CONTROLLERS
SGUS036B − JULY 2003 − REVISED OCTOBER 2003
input qualifier circuitry
An input-qualifier circuitry qualifies the input signal to the CAP1−6, XINT1/2, ADCSOC and PDPINTA/B pins
in the 240xA devices. (The I/O functions of these pins do not use the input-qualifier circuitry). The state of the
internal input signal will change only after the pin is high/low for 6(12) clock edges. This ensures that a glitch
smaller than 5(11) CLKOUT cycles wide will not change the internal pin input state. The user must hold the pin
high/low for 6(12) cycles to ensure the device will see the level change. Bit 6 of the SCSR2 register controls
whether 6 clock edges (bit 6 = 0) or 12 clock edges (bit 6 = 1) are used to block 5- or 11-cycle glitches. On the
LC2402A, input qualification is for the CAP1, CAP2, CAP3, PDPINTA, and XINT2/ADCSOC pins.
enhanced analog-to-digital converter (ADC) module
A simplified functional block diagram of the ADC module is shown in Figure 5. The ADC module consists of a
10-bit ADC with a built-in sample-and-hold (S / H) circuit. Functions of the ADC module include:
D 10-bit ADC core with built-in S/H
D 16-channel, MUXed inputs
D Autosequencing capability provides up to 16 “autoconversions” in a single session. Each conversion can
be programmed to select any 1 of 16 input channels
D Sequencer can be operated as two independent 8-state sequencers or as one large 16-state sequencer
(i.e., two cascaded 8-state sequencers)
D Sixteen result registers (individually addressable) to store conversion values
− The digital value of the input analog voltage is derived by:
Digital Value + 1023
Input Analog Voltage * V_REFLO
V_REFHI * V_REFLO
D Multiple triggers as sources for the start-of-conversion (SOC) sequence
− S/W − software immediate start
− EVA − Event manager A (multiple event sources within EVA)
− EVB − Event manager B (multiple event sources within EVB)
− Ext − External pin (ADCSOC)
D Flexible interrupt control allows interrupt request on every end-of-sequence (EOS) or every other EOS
D Sequencer can operate in “start/stop” mode, allowing multiple “time-sequenced triggers” to synchronize
conversions
D EVA and EVB triggers can operate independently in dual-sequencer mode
D Sample-and-hold (S/H) acquisition time window has separate prescale control
NOTE: The calibration and self-test features are not present in 240xA devices.
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