SM320LF2407-EP Datasheet, PDF (65/112 Pages) Texas Instruments – 
DSP CONTROLLERS

SM320LF2407AĆEP
DSP CONTROLLERS
SGUS036B − JULY 2003 − REVISED OCTOBER 2003
RS timings
timing requirements for a reset [H = 0.5t_c(CO)] (see Figure 20 and Figure 21)
tw(RSL)
tw(RSL2)
tp
td(EX)
Pulse duration, stable CLKIN to RS high
Pulse duration, RS low
PLL lock-up time
Delay time, reset vector executed after PLL lock time
MIN
8tc(CI)
8tc(CI)
NOM
MAX
4096tc(CI)
36H
UNIT
cycles
cycles
ns
ns
VDD/VDDO
RS
tp
tw(RSL)
td(EX)
CLKIN
XTAL1†
BOOT_EN
/XF
tOSCST‡
BOOT_EN
XF
CLKOUT
I/Os
Hi-Z
Code-Dependent
Address/
Data/
Control
† _{XTAL1 refers to internal oscillator clock if on-chip oscillator is used.}
‡ _{tOSCST is the oscillator start-up time, which is dependent on crystal/resonator and board design.}
Figure 20. Power-on Reset
Address/Data/Control Valid
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