TI380C30 Datasheet, PDF (9/78 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30
INTEGRATED TOKEN-RING
COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE
SPWS016A – NOVEMBER 1994 – REVISED JULY 1995
Pin Functions (Continued)
PIN
NAME
NO.
I/O/E^†
DESCRIPTION
RATER
RATER indicates that there are transitions on the RCV+ / RCV– input pair (DRVR +/ DRVR – if WRAP
158
O
is asserted low) but that the transition rate is not consistent with the ring speed selected by the S4 / 16
pin.
RCLK
161
O
Recovered clock. RCLK is the clock recovered from the token-ring received data. For 16-Mbps
operation, it is a 32-MHz clock. For 4-Mbps operation, it is an 8-MHz clock.
RCV+
RCV–
149
I
Receiver. RCV+ and RCV– are differential inputs that receive the token-ring data via isolation
147
I
transformers.
RCVR
162
O
Recovered data. RCVR contains the data recovered from the token ring.
REDY
PLL ready. REDY is normally asserted (active) low. It is cleared following the assertion of FRAQ and
124
O
reasserted after the data recovery PLL has been reinitialized.
H = Received data not valid
L = Received data valid
RES
137
—
Reserved. Should be left unconnected.
SADH0
SADH1
SADH2
SADH3
SADH4
SADH5
SADH6
SADH7
110
System address/data bus — high byte (see Note 1).These lines make up the most significant byte of
109
each address word (32-bit address bus) and data word (16-bit data bus). The most significant bit is
108
SADH0, and the least significant bit is SADH7.
107
106
I/O
Address multiplexing: Bits 31 – 24 and bits 15 – 8 ^‡
105
Data multiplexing: Bits 15 – 8 ^‡
101
100
SADL0
SADL1
SADL2
SADL3
SADL4
SADL5
SADL6
SADL7
91
System address/data bus — low byte (see Note 1). These lines make up the least significant byte of
90
each address word (32-bit address bus) and data word (16-bit data bus). The most significant bit is
89
SADL0, and the least significant bit is SADL7.
86
85
I/O
Address multiplexing: Bits 23 – 16 and bits 7 – 0 ^‡
84
Data multiplexing : Bits 7 – 0 ^‡
83
82
SALE
System address-latch enable. SALE is the enable pulse used to externally latch the 16 LSBs of the
80
O
address from the SADH0 – SADH7 and SADL0 – SADL7 buses at the start of the DMA cycle. Systems
that implement address parity can also externally latch the parity bits (SPH and SPL) for the latched
address.
SBBSY
System bus busy. The TI380C30 samples the value on SBBSY during arbitration (see Note 1). The
sample has one of two values:
68
I
H = Not busy. The TI380C30 can become bus master if the grant condition is met.
L = Busy. The TI380C30 cannot become bus master.
SBCLK
81
I
System bus clock. The TI380C30 requires the external clock to synchronize its bus timings for all DMA
transfers. Valid frequencies are 2 MHz – 33 MHz.
SBHE is used for system byte high enable. SBHE is a 3-state output driven during DMA;
it is an input at all other times.
Intel Mode
H = System byte high not enabled (see Note 1)
SBHE / SRNW
94
I/O
L = System byte high enabled
SRNW is used for system read not write. SRNW serves as a control signal to indicate
Motorola ^{a read or write cycle.}
Mode _{H = Read cycle (see Note 1)}
L = Write cycle
† _{I = input, O = output, E = provides external-component connection to the internal circuitry for tuning}
‡ _{Typical bit ordering for Intel™ and Motorola processor buses}
NOTE 1: Pin has an internal pullup device to maintain a high-voltage level when left unconnected (no etch).
Intel is a trademark of Intel Corporation.
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