TI380C30 Datasheet, PDF (11/78 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30
INTEGRATED TOKEN-RING
COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE
SPWS016A – NOVEMBER 1994 – REVISED JULY 1995
Pin Functions (Continued)
PIN
NAME
NO.
I/O/E†
DESCRIPTION
System-Intel / Motorola mode select. The value on SI / M specifies the system-interface mode.
SI / M
72
SINTR / SIRQ
73
SOWN
96
SPH
99
SPL
92
I
H = Intel-compatible-interface mode selected. Intel interface can be 8-bit or 16-bit mode
(see S8 / SHALT description and Note 1).
L = Motorola-compatible-interface mode selected. Motorola-interface mode is always 16 bits.
SINTR is used for system-interrupt request. TI380C30 activates SINTR to signal an
interrupt request to the host processor.
Intel Mode
H = Interrupt request by TI380C30
L = No interrupt request
O
SIRQ is used for system-interrupt request. TI380C30 activates SIRQ to signal an
Motorola ^{interrupt request to the host processor.}
Mode _{H = No interrupt request}
L = Interrupt request by TI380C30
System bus owned. SOWN indicates to external devices that TI380C30 has control of the system bus.
SOWN drives the enable signal of the bus-transceiver chips that drive the address and bus-control
O
signals.
H = TI380C30 does not have control of the system bus.
L = TI380C30 has control of the system bus.
I/O
System parity high. SPH is the optional odd-parity bit for each address or data byte transmitted over
SADH0 – SADH7 (see Note 1).
I/O
System parity low. SPL is the optional odd-parity bit for each address or data byte transmitted over
SADL0 – SADL7 (see Note 1).
Intel Mode
SRAS is used for system memory-address strobe (see Note 7). SRAS is used to latch
the SCS and SRSX – SRS2 register input signals. In a minimum-chip system, SRAS is
tied to the SALE output of the system bus. The latching capability can be defeated since
the internal latch for these inputs remains transparent as long as SRAS remains high.
This permits SRAS to be pulled high and the signals at SCS, SRSX – SRS2, and SBHE
to be applied independently of the SALE strobe from the system bus. During DMA, SRAS
remains an input.
SRAS / SAS
76
I/O
H
= Transparent mode
L
= Holds latched values of SCS, SRSX – SRS2, and SBHE
Falling edge = Latches SCS, SRSX – SRS2, and SBHE
SAS is used for sytem-memory address strobe (see Note 7). SAS is an active-low
address strobe that is an input during DIO (although ignored as an address strobe) and
Motorola an output during DMA.
Mode
H = Address is not valid.
L = Address is valid and a transfer operation is in progress.
† _{I = input, O = output, E = provides external-component connection to the internal circuitry for tuning}
NOTES: 1. Pin has an internal pullup device to maintain a high-voltage level when left unconnected (no etch).
7. Pin should be tied to VDD with a 4.7-kΩ pullup resistor.
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