TI380C30 Datasheet, PDF (51/78 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30
INTEGRATED TOKEN-RING
COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE
SPWS016A – NOVEMBER 1994 – REVISED JULY 1995
80x8x interrupt-acknowledge-cycle timing: first SIACK pulse
25-MHz
33-MHz
NO.
OPERATION
OPERATION
UNIT
MIN
MAX MIN
MAX
286 Pulse duration, SIACK high between DIO accesses (see Note 25)
tc(SCK)
tc(SCK)
ns
287 Pulse duration, SIACK low on first pulse of two pulses
tc(SCK)
tc(SCK)
ns
NOTE 25: The inactive chip select is SIACK in DIO-read and DIO-write cycles, and SCS is the inactive chip select in interrupt-acknowledge cycles.
SRD, SWR,
SCS
SIACK
287
First
286
Second
Figure 21. 80x8x Interrupt-Acknowledge-Cycle Timing: First SIACK Pulse
80x8x interrupt-acknowledge-cycle timing: second SIACK pulse
25-MHz OPERATION
33-MHz OPERATION
NO.
UNIT
MIN
MAX
MIN
MAX
255 Delay time, SRDY low to SCS high
15
15
ns
259†
Hold time, SAD in the high-impedance state after SIACK low
(see Note 25)
0
0
ns
260 Setup time, output data valid before SRDY low
0
0
ns
261†
Delay time, SIACK high to SAD in the high-impedance state
(see Note 25)
35
35
ns
261a Hold time, output data valid after SIACK high (see Note 25)
0
0
ns
272a
273a
275
Setup time, inactive data strobe high to SIACK no longer high
Hold time, inactive data strobe high after SIACK high
Delay time, SIACK high to SRDY high (see Note 25)
tc(SCK)
tc(SCK)
0
tc(SCK)
tc(SCK)
25
0
ns
ns
25
ns
276‡
Delay time, SRDY low in the first DIO access to the SIF register
to SRDY low in the immediately following access to the SIF
4000
4000
ns
279†
282a
282R
Delay time, SIACK high to SRDY in the high-impedance state
Delay time, SDBEN low to SRDY low in a read cycle
Delay time, SIACK low to SDBEN low (see TMS380 Second
Generation Token-Ring User’s Guide, SPWU005, subsection
3.4.1.1.1), provided previous cycle completed
0
tc(SCK)
0 tc(SCK) / 2 + 4
0
tc(SCK) + 3
0
tc(SCK)
ns
0 tc(SCK) / 2 + 4 ns
0
tc(SCK) + 3 ns
283R Delay time, SIACK high to SDBEN high (see Note 25)
0 tc(SCK) / 2 + 4
0 tc(SCK) / 2 + 4 ns
† _{This specification is provided as an aid to board design. It is not assured during manufacturing.}
‡ _{This specification has been characterized to meet stated value. It is not assured during manufacturing.}
NOTE 25: The inactive chip select is SIACK in DIO-read and DIO-write cycles; SCS is the inactive chip select in interrupt-acknowledge cycles.
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
51