TI380C30 Datasheet, PDF (3/78 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30
INTEGRATED TOKEN-RING
COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE
SPWS016A – NOVEMBER 1994 – REVISED JULY 1995
description
The TI380C30 is a single-chip token-ring solution, combining both the commprocessor and the physical-layer
interface onto a single device. The TI380C30 supports both 16 and 4 Mbps of operation, conforms to ISO
8802–5/ IEEE 802.5 – 1992 standards, and has been verified to be completely IBM Token-Ring Network
compatible.
The TI380C30 provides a high degree of integration as it combines the functions of the TI380C25 and the
TI380C60 onto a single chip. With this chip, only local memory and minimal additional components such as
PAL^® devices and crystal oscillators need to be added to complete the LAN-subsystem design.
The TI380C30 provides a 32-bit system-memory address reach with a high-speed bus-master DMA interface
that supports rapid communications with the host system. In addition, the TI380C30 supports direct I/O and a
low-cost 8- or 16-bit pseudo-DMA interface that requires only a chip select to work directly on an 80x8x 8-bit
slave I/O interface. Selectable 80x8x or 68xxx-type host-system bus and memory organization add to design
flexibility.
The TI380C30 supports addressing for up to 2 Mbytes of local memory. This expanded memory capacity can
improve LAN-subsystem performance by minimizing the frequency of host LAN-subsystem communications
by allowing larger blocks of information to be transferred at one time. The support of large local memory is
important in applications that require large data transfers (such as graphics or data-base transfers) and in
heavily loaded networks where the extra memory can provide data buffers to store data until it can be processed
by the host.
The proprietary CPU used in the TI380C30 allows protocol software to be downloaded into RAM or stored in
ROM in the local-memory space. By moving protocols [such as logical link control (LLC)] to the LAN-subsystem,
overall system performance is increased. This is accomplished by offloading processing from the host-system
to the TI380C30, which can also reduce LAN-subsystem-to-host communications. As other protocol software
is developed, greater differentiation of end products with enhanced system performance is possible.
The TI380C30 includes hardware counters that provide real-time error detection and automatic frame-buffer
management. These counters control system-bus retries and burst size, and track host- and
LAN-subsystem-buffer status. Previously, these counters needed to be maintained in software. By integrating
them into hardware, software overhead is removed and LAN-subsystem performance is improved.
The TI380C30 implements a TI-patented enhanced-address-copy-option (EACO) interface. This interface
supports external address-checking devices, such as the TMS380SRA source-routing accelerator. The
TI380C30 has a 128-word external I/O space in its memory to support external address-checker devices and
other hardware extensions to the TMS380 architecture.
At the physical-layer interface, the Manchester-encoded data stream is received and phase aligned using an
on-chip dual-digital phase-locked loop (PLL). Both the recovered clock and data are passed on to the
protocol-handling circuits on the TI380C30 for serial-to-parallel conversion and data processing. On transmit,
the TI380C30 buffers the output from the protocol-handling circuit and drives the media via suitable isolation
and waveform-shaping components.
The TI380C30 uses CMOS technology to reduce power consumption to PCMCIA-compatible levels.
Power-management features are incorporated to support Green PC compatibility.
In addition to the PLL, all other functions required to interface to an IEEE-802.5 token ring are provided. These
functions include the phantom drive to control the relays within a trunk-coupling unit and wire-fault detection
circuits; an internal-wrap function for self-test ; and a watchdog timer to provide fail-safe deinsertion from the
ring in the event of a station, microcode or commprocessor failure.
The major blocks of the TI380C30 include the communications processor (CP), the system interface (SIF), the
memory interface (MIF), the protocol handler (PH), the clock generator (CG), the adapter-support function
(ASF), and the physical-layer interface (PHY), as shown in the functional block diagram.
PAL^® is a registered trademark of Advanced Micro Devices Inc. Other companies also manufacture programmable array logic devices.
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