TI380C30 Datasheet, PDF (35/78 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30
INTEGRATED TOKEN-RING
COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE
SPWS016A – NOVEMBER 1994 – REVISED JULY 1995
power up, SBCLK, OSCIN, MBCLK1, MBCLK2, SYNCIN, and SRESET timing
NO.
100†
101†‡
102†‡
103
104
105
106†
107
tr(VDD)
td(VDDH-SCKV)
td(VDDH-OSCV)
tc(SCK)
tw(SCKH)
tw(SCKL)
tt(SCK)
tc(OSC)
Rise time, 1.2 V to minimum VDD-high level
Delay time, minimum VDD-high level to first valid SBCLK no longer high
Delay time, minimum VDD-high level to first valid OSCIN high
Cycle time, SBCLK (see Note 19)
Pulse duration, SBCLK high
Pulse duration, SBCLK low
Transition time, SBCLK
Cycle time, OSCIN (see Note 20)
OSCIN = 64 MHz
MIN NOM
30.3
13
13
1 / OSCIN
5.5
MAX
1
1
1
500
500
500
2
UNIT
ms
ms
ms
ns
ns
ns
ns
ns
108 tw(OSCH)
Pulse duration, OSCIN high (see Note 21)
OSCIN = 48 MHz
8
ns
OSCIN = 32 MHz
8
OSCIN = 64 MHz
5.5
109 tw(OSCL)
Pulse duration, OSCIN low (see Note 21)
OSCIN = 48 MHz
8
ns
OSCIN = 32 MHz
8
110† tt(OSC)
Transition time, OSCIN
111† td(OSCV-CKV) Delay time, OSCIN valid to MBCLK1 and MBCLK2 valid
117† th(VDDH-RSL)
Hold time, SRESET low after VDD reaches minimum high level
5
118† tw(RSH)
Pulse duration, SRESET high
14
119† tw(RSL)
Pulse duration, SRESET low
14
288† tsu(RST)
Setup time, DMA size to SRESET high (Intel mode only)
10
289† th(RST)
Hold time, DMA size from SRESET high (Intel mode only)
10
3 ns
1 ms
ms
µs
µs
ns
ns
CLKDIV = H
2tc(OSC)
tM
One-eighth of a local-memory cycle
ns
CLKDIV = L
2tc(OSC)
† _{This specification is provided as an aid to board design. It is not assured during manufacturing testing.}
‡ _{If parameter 101 or 102 cannot be met, parameter 117 must be extended by the larger difference: real value of parameter 101 or 102 minus the}
max value listed.
NOTES: 19. SBCLK can be any value between 2 MHz and 33 MHz. This data sheet describes the system interface ( SIF ) timing parameters for
the cases of SBCLK at 25 MHz and 33 MHz.
20. The value of OSCIN can be 64 MHz ±1%, 32 MHz ± 1%, or 48 MHz ± 1%. If OSCIN is used to generate PXTALIN, the OSCIN
tolerance must be ± 0.01%.
21. This is to assure a ± 5% duty-cycle crystal, provided that OSCIN meets the recommended operating conditions for VIH and VIL .
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