TI380C30 Datasheet, PDF (25/78 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30
INTEGRATED TOKEN-RING
COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE
SPWS016A – NOVEMBER 1994 – REVISED JULY 1995
SIF adapter-control register (SIFACL) (continued)
Bit 5:
SWDDIR — Current SDDIR-Signal Value
Contains the current value of the pseudo-DMA direction. This enables the host to easily
determine the direction of DMA transfers, which allows system DMA to be controlled by system
software.
0 = Pseudo DMA from host system to TI380C30
1 = Pseudo DMA from TI380C30 to host system
Bit 6:
SWHRQ — Current SHRQ-Signal Value
Contains the current value on SHRQ / SBRQ when in Intel mode and the inverse of the value on
SHRQ/ SBRQ in Motorola mode. This enables the host to easily determine if a pseudo-DMA
transfer is requested.
INTEL MODE (SI / M = H)
0 = System bus not requested
1 = System bus requested
MOTOROLA MODE (SI / M = L)
1 = System bus not requested
0 = System bus requested
Bit 7:
Bit 8:
Bit 9:
Bit 10:
PSDMAEN — Pseudo-System-DMA Enable
Enables pseudo-DMA operation
0 = Normal bus-master DMA operation is possible.
1 = Pseudo-DMA operation selected. Operation dependent on the values of the SWHLDA and
SWHRQ bits in the SIFACL register.
ARESET — Adapter Reset
Is a hardware reset of the TI380C30. This bit has the same effect as SRESET except that the
DIO interface to the SIFACL register is maintained. This bit is set to 1 if a clock failure is detected
(OSCIN, PXTALIN, RCLK, or SBCLK not valid).
0 = The TI380C30 operates normally.
1 = The TI380C30 is held in the reset condition.
CPHALT — Communications-Processor Halt
Controls the TI380C30 processor access to the internal TI380C30 buses. This prevents the
TI380C30 from executing instructions before the microcode is downloaded.
0 = The TI380C30 processor can access the internal TI380C30 buses.
1 = The TI380C30 processor cannot access the internal-adapter buses.
BOOT — Bootstrap CP Code
Indicates whether the memory in chapters 0 and 31 of the local-memory space is RAM or
ROM/ PROM/ EPROM. This bit controls the operation of MCAS and MROMEN.
0 = ROM/ PROM/ EPROM memory in chapters 0 and 31
1 = RAM memory in chapters 0 and 31
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