TI380C30 Datasheet, PDF (46/78 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30
INTEGRATED TOKEN-RING
COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE
SPWS016A – NOVEMBER 1994 – REVISED JULY 1995
token ring: transmitter timing
NO.
MIN MAX UNIT
159 tsk(DR)
Delay time, DRVR rising edge (1.8 V ) to DRVR falling edge (1 V ) or DRVR falling edge
(1 V ) to DRVR rising edge (1.8 V )
±2 ns
160 td(DR)H†
Delay time, RCLK (or PXTALIN) falling edge (1 V ) to DRVR rising edge (1.8 V )
See Note 24 ns
161 td(DR)L†
Delay time, RCLK (or PXTALIN) falling edge (1 V ) to DRVR falling edge (1 V )
See Note 24 ns
162 td(DRN)H†
Delay time, RCLK (or PXTALIN) falling edge (1 V ) to DRVR falling edge (1 V )
See Note 24 ns
163 t(DRN)L†
Delay time, RCLK (or PXTALIN) falling edge (1 V ) to DRVR rising edge (1.8 V )
164
DRVR / DRVR
asymmetry
) ) t_d(DR)L
t_d(DRN)H
2
– ^td(DR)H
t_d(DRN)L
2
See Note 24 ns
±1.5 ns
† _{When in active-monitor mode, the clock source is PXTALIN; otherwise, the clock-source is either RCLK or PXTALIN.}
NOTE 24: This parameter is not tested to a minimum or a maximum but is measured and used as a component required for parameter 164.
RCLK or PXTALIN
2.6 V
1.5 V
0.6 V
DRVR
DRVR
160
159
162
161
159
163
2.4 V
1.5 V
0.6 V
2.4 V
1.5 V
0.6 V
Figure 18. Skew and Asymmetry From RCLK or PXTALIN to DRVR and DRVR
46
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