TI380C30 Datasheet, PDF (75/78 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30
INTEGRATED TOKEN-RING
COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE
SPWS016A – NOVEMBER 1994 – REVISED JULY 1995
68xxx-mode bus-release and error timing
NO.
208a Setup time, asynchronous input before SBCLK no longer high to assure recognition
208b
Hold time, asynchronous input SBRLS, SOWN, or SBERR after SBCLK low to assure
recognition
208c Hold time, SBRLS low after SOWN high
236 Setup time, SBERR low before SDTACK no longer high if parameter 208a not met
25-MHz
OPERATION
MIN MAX
10
10
0
30
33-MHz
OPERATION
MIN MAX
10
10
0
30
UNIT
ns
ns
ns
ns
T(W or 2)
T3
T4
T1
T2
SBCLK ^†
SBRLS ^‡
208a
208b
SOWN
SBERR ^§
208a
208b
208c
236
SDTACK
† _{Unless otherwise specified, for all signals specified as a maximum delay from the end of an SBCLK transition to the signal valid, the signal is}
also specified to hold its previous value (including high impedance) until the start of that SBCLK transition.
‡ _{The system interface ignores the assertion of SBRLS if it does not own the system bus. If it does own the bus, when it detects the assertion of}
SBRLS, it completes any internally-started DMA cycle and relinquishes control of the bus. If no DMA transfer has started internally, the system
interface releases the bus before starting another.
§ _{If SBERR is asserted when the system interface controls the system bus, the current bus transfer is completed, regardless of the value of}
SDTACK. If the BERETRY register is nonzero, the cycle is retried. If the BERETRY register is zero, the system interface then releases control
of the system bus. The system interface ignores the assertion of SBERR if it is not performing a DMA-bus cycle on the system bus. When SBERR
is properly asserted and BERETRY is zero, however, the system interface releases the bus upon completion of the current bus transfer and halts
all further DMA on the system side. The error is synchronized to the local bus and DMA stops on the local sides. The value of the SDMAADR,
SDMADDRX, and SDMALEN registers in the system interface are not defined after a system-bus error.
Figure 35. 68xxx-Mode Bus-Release and Error Timing
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