TI380C30 Datasheet, PDF (30/78 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30
INTEGRATED TOKEN-RING
COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE
SPWS016A – NOVEMBER 1994 – REVISED JULY 1995
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
PLL characteristics
VFILT
PARAMETER
Reference PLL operating filter voltage
TEST CONDITIONS
tc(XT1) = 125 ns
MIN MAX UNIT
1.8 4.0 V
crystal-oscillator characteristics
PARAMETER
VSB(XT1) Input self-bias voltage
IOH(XT2) Output high-level current
IOL(XT2) Output low-level current
TEST CONDITIONS
V(XT2) = VSB(XT1)
V(XT1) = VSB(XT1) + 0.5 V
V(XT2) = VSB(XT1)
V(XT1) = VSB(XT1) – 0.5 V
MIN MAX UNIT
1.8 4.0 V
– 2.5 – 6.5 mA
0.4 1.3 mA
timing parameters
The timing parameters for the signals of TI380C30 are shown in the following tables and are illustrated in the
accompanying figures. The purpose of these figures and tables is to quantify the timing relationships among
the various signals. The parameters are numbered for convenience.
static signals
The following table lists signals that are not allowed to change dynamically and therefore have no timing
associated with them. They should be strapped high, low, or left unconnected as required.
SIGNAL
FUNCTION
SI / M
Host-processor select (Intel / Motorola)
CLKDIV
Reserved
BTSTRP
Default-bootstrap mode (RAM / ROM)
PRTYEN
Default-parity select (enabled / disabled)
TEST0
Test pin indicates network type
TEST1
NC
TEST2
Test pin indicates network type
TEST3
Test pin for TI manufacturing test ^†
TEST4
Test pin for TI manufacturing test ^†
TEST5
Test pin for TI manufacturing test ^†
† _{For unit-in-place test}
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