TI380C30 Datasheet, PDF (49/78 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30
INTEGRATED TOKEN-RING
COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE
SPWS016A – NOVEMBER 1994 – REVISED JULY 1995
80x8x DIO write-cycle timing
25-MHz OPERATION
33-MHz OPERATION
NO.
UNIT
MIN
MAX
MIN
MAX
255 Delay time, SRDY low to either SCS or SWR high
15
15
ns
256 Pulse duration, SRAS high
30
30
ns
Setup time, SADH0 – SADH7, SADL0 – SADL7, SPH, and SPL
262 _{valid before SCS or SWR no longer low}
15
15
ns
263
Hold time, SADH0 – SADH7, SADL0 – SADL7, SPH, and SPL
valid after SCS or SWR high
15
15
ns
264
Setup time, SRSX, SRS0 – SRS2, SCS, and SBHE to SRAS no
longer high (see Note 26)
30
30
ns
265
Hold time, SRSX, SRS0 – SRS2, SCS, and SBHE after SRAS
low
10
10
ns
266a Setup time, SRAS high to SWR no longer high (see Note 25)
15
15
ns
267†
Setup time, SRSX, SRS0 – SRS2 before SWR no longer high
(see Note 25)
15
15
ns
268
Hold time, SRSX, SRS0 – SRS2 valid after SWR no longer low
(see Note 26)
0
0
ns
272a
Setup time, SRD, SWR, and SIACK high from previous cycle to
SWR no longer high
tc(SCK)
tc(SCK)
ns
273a Hold time, SRD, SWR, and SIACK high after SWR high
tc(SCK)
tc(SCK)
ns
Delay time, SRDY low in the first DIO access to the SIF register
276‡
to SRDY low in the immediately following access to the SIF
(see TMS380 Second-Generation Token-Ring User’s Guide,
SPWU005, subsection 3.4.1.1.1)
4000
4000
275
279§
280
282b
Delay time, SWR or SCS high to SRDY high (see Note 25)
Delay time, SWR high to SRDY in the high-impedance state
Delay time, SWR low to SDDIR low (see Note 25)
Delay time, SDBEN low to SRDY low (see
TMS380 Second Generation Token-Ring
User’s Guide, SPWU005, subsection
3.4.1.1.1)
If SIF register is
ready (no waiting
required)
If SIF register is
not ready (waiting
required)
0
25
0
tc(SCK)
0 tc(SCK) / 2 + 4
0 tc(SCK) / 2 + 4
0
4000
0
25
ns
0
tc(SCK) ns
0 tc(SCK) / 2 + 4 ns
0 tc(SCK) / 2 + 4
ns
0
4000
282W Delay time, SDDIR low to SDBEN low
0 tc(SCK) / 2 + 4
0 tc(SCK) / 2 + 4 ns
283W Delay time, SCS or SWR high to SDBEN no longer low
0 tc(SCK) / 2 + 4
0 tc(SCK) / 2 + 4 ns
286 Pulse duration, SWR high between DIO accesses (see Note 25) tc(SCK)
tc(SCK)
ns
† _{It is the later of SRD and SWR or SCS low that indicates the start of the cycle.}
‡ _{This specification has been characterized to meet stated value. It is not assured during manufacturing testing.}
§ _{This specification is provided as an aid to board design. It is not assured during manufacturing testing.}
NOTES: 25. The inactive chip select is SIACK in DIO-read and DIO-write cycles; SCS is the inactive chip select in interrupt-acknowledge cycles.
26. In 80x8x mode, SRAS can be used to strobe the values of SBHE, SRSX, SRS0 – SRS2, and SCS. When used to do so, SRAS must
meet parameter 266a; SBHE, SRS0 – SRS2, and SCS must meet parameter 264. If SRAS is strapped high, parameters 266a and
264 are irrelevant and parameter 268 must be met.
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