TI380C30 Datasheet, PDF (8/78 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30
INTEGRATED TOKEN-RING
COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE
SPWS016A – NOVEMBER 1994 – REVISED JULY 1995
Pin Functions (Continued)
PIN
NAME
NO.
I/O/E^†
DESCRIPTION
NABL
156
I
Output-enable control. NABL is used in the physical-layer circuitry (see Note 1).
NC
135
166
These pins should be left unconnected.
NMI
55
I
Nonmaskable interrupt request. NMI must be left unconnected.
Network selection outputs. NSELOUT0 and NSELOUT1 are controlled by the host through the
corresponding bits of the SIFACL register. The value of NSELOUT0 and NSELOUT1 can be changed
NSELOUT0
58
O
only while the TI380C30 is reset.
NSELOUT1
171
O
NSELOUT0
NSELOUT1
DESCRIPTION
L
H
16-Mbps token ring
H
H
4-Mbps token ring
NSRT
Insert control. NSRT enables the phantom-driver outputs (PHOUTA and PHOUTB) through the
watchdog timer for insertion onto the token ring.
121
O
Static high = Inactive, phantom current removed (due to watchdog timer)
Static low = Inactive, phantom current removed (due to watchdog timer)
Falling edge = Active, current output on PHOUTA and PHOUTB
OSC32
5
O
Oscillator output . OSC32 provides a 32-MHz clock output and can be used to drive OSCIN and one
other TTL load.
OSCIN
External oscillator input. OSCIN provides the clock frequency to the TI380C30 for a 4-MHz or 6-MHz
internal bus (see Notes 5 and 6).
6
I
CLKDIV OSCIN
H
64 MHz for a 4-MHz local bus
L
32 MHz for a 4-MHz local bus or 48 MHz for a 6-MHz local bus
OSCOUT
Oscillator output
CLKDIV OSCOUT
172
O
L
OSCIN ÷ 4 (if OSCIN = 32 MHz, OSCOUT = 8 MHz;
if OSCIN = 48 MHz, OSCOUT = 12 MHz)
H
OSCIN ÷ 8 (if OSCIN = 64 MHz, OSCOUT = 8 MHz)
PHOUTA
PHOUTB
139
141
O
O
Phantom-driver outputs A and B. PHOUTA and PHOUTB cause insertion onto the token ring. PHOUTA
and PHOUTB should be connected to the center tap of the transmit transformer secondary winding
for phantom-drive generation.
PRTYEN
Parity enable. The value on PRTYEN is loaded into the PEN bit of the SIFACL register at reset (i.e.,
when SRESET is asserted or the ARESET bit in the SIFACL register is set) to form a default value.
59
I
PRTYEN enables parity checking for the local memory.
H = Local-memory data bus checked for parity (see Note 1).
L = Local-memory data bus not checked for parity.
PWRDN
Power-down control (see Note 7)
154
I
H = Normal operation
L = TI380C30 physical-layer circuitry is placed into a power-down state. All TTL outputs of the
physical layer are driven to the high-impedance state.
PXTAL
163
O
Reference-clock output. PXTAL is synthesized from the 8-MHz crystal oscillator used for XT1 and XT2.
For 16 Mbps it is a 32-MHz clock, for 4 Mbps it is a 8-MHz clock.
† _{I = input, O = output, E = provides external-component connection to the internal circuitry for tuning}
NOTES: 1. Pin has an internal pullup device to maintain a high-voltage level when left unconnected (no etch).
3. Each pin must be individually tied to VDD with a 1-kΩ pullup resistor.
5. Pin has an expanded input voltage specification.
6. A maximum of two TI380C30 devices can be connected to any one oscillator.
7. Pin should be tied to VDD with a 4.7-kΩ pullup resistor.
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