TI380C30 Datasheet, PDF (31/78 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30
INTEGRATED TOKEN-RING
COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE
SPWS016A – NOVEMBER 1994 – REVISED JULY 1995
timing parameter symbology
Some timing parameter symbols have been created in accordance with JEDEC Standard 100-A. To shorten
the symbols, some of the signal names and other related terminology have been abbreviated as shown below:
DR
DRN
OSC
SCK
DRVR
DRVR
OSCIN
SBCLK
Lower-case subscripts are defined as follows:
RS
VDD
SRESET
VDDL, VDD
c
cycle time
d
delay time
h
hold time
w
pulse duration (width)
r
rise time
sk
skew
su
setup time
t
transition time
The following additional letters and phrases are defined as follows:
H
High
L
Low
V
Valid
Z
Falling edge
Rising edge
High impedance
No longer high
No longer low
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