TI380C30 Datasheet, PDF (47/78 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30
INTEGRATED TOKEN-RING
COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE
SPWS016A – NOVEMBER 1994 – REVISED JULY 1995
80x8x DIO read-cycle timing
25-MHz OPERATION
33-MHz OPERATION
NO.
UNIT
MIN
MAX
MIN
MAX
255 Delay time, SRDY low to either SCS or SRD high
15
15
ns
256 Pulse duration, SRAS high
30
30
ns
259†
Hold time, SAD in the high-impedance state after SRD low
(see Note 25)
0
0
ns
260
Setup time, SADH0 – SADH7, SADL0 – SADL7, SPH, and
SPL valid before SRDY low
0
0
ns
261†
Delay time, SRD or SCS high to SAD in the high-impedance
state (see Note 25)
35
35
ns
261a
Hold time, output data valid after SRD or SCS high
(see Note 25)
0
0
ns
Setup time, SRSX, SRS0 – SRS2, SCS, and SBHE valid to
264
SRAS no longer high (see Note 26)
30
30
ns
265
Hold time, SRSX, SRS0 – SRS2, SCS, and SBHE valid after
SRAS low
10
10
ns
266a Setup time, SRAS high to SRD no longer high (see Note 26) 15
15
ns
267‡
Setup time, SRSX, SRS0 – SRS2 valid before SRD no longer
high (see Note 25)
15
15
ns
268
Hold time, SRSX, SRS0 – SRS2 valid after SRD no longer low
(see Note 26)
0
0
ns
272a
Setup time, SRD, SWR, and SIACK high from previous cycle
to SRD no longer high
tc(SCK)
tc(SCK)
ns
273a
275
Hold time, SRD, SWR, and SIACK high after SRD high
Delay time, SRD and SWR, or SCS high to SRDY high
(see Note 25)
tc(SCK)
0
tc(SCK)
25
0
ns
25
ns
279†
Delay time, SRD and SWR, high to SRDY in the
high-impedance state
0
tc(SCK)
0
tc(SCK) ns
282a Delay time, SDBEN low to SRDY low in a read cycle
0
tc(SCK) / 2 + 4
0
tc(SCK) / 2 + 4 ns
Delay time, SRD low to SDBEN low (see TMS380 Second
282R Generation Token-Ring User’s Guide, SPWU005, subsection
0
3.4.1.1.1), provided previous cycle completed
tc(SCK) + 3
0
tc(SCK) + 3 ns
283R Delay time, SRD high to SDBEN high (see Note 25)
0
tc(SCK) / 2 + 4
0
tc(SCK) / 2 + 4 ns
286
Pulse duration, SRD high between DIO accesses
(see Note 25)
tc(SCK)
tc(SCK)
ns
† _{This specification is provided as an aid to board design. It is not assured during manufacturing testing.}
‡ _{It is the later of SRD and SWR or SCS low that indicates the start of the cycle.}
NOTES: 25. The inactive chip select is SIACK in DIO-read and DIO-write cycles, and SCS is the inactive chip select in interrupt-acknowledge
cycles.
26. In 80x8x mode, SRAS can be used to strobe the values of SBHE, SRSX, SRS0 – SRS2, and SCS. When used to do so, SRAS must
meet parameter 266a, and SBHE, SRS0 – SRS2, and SCS must meet parameter 264. If SRAS is strapped high, parameters 266a
and 264 are irrelevant and parameter 268 must be met.
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