TI380C30 Datasheet, PDF (18/78 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30
INTEGRATED TOKEN-RING
COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE
SPWS016A – NOVEMBER 1994 – REVISED JULY 1995
adapter-support function (ASF)
The ASF performs support functions not contained in the other blocks. The features are:
D The TI380C30 base timer
D Identification, management, and service of internal and external interrupts
D Test-pin mode control, including the unit-in-place mode for board testing
D Checks for illegal states, such as illegal opcodes and parity
clock generator (CG)
The CG performs the generation of all internal clocks required by the other functional blocks, including the local
memory-bus clocks (MBCLK1, MBCLK2). The CG also generates the reference timer used to sample all input
clocks (SBCLK, OSCIN, RCLK, and PXTALIN). If no transition is detected within the period of the reference timer
on any input clock signal, the CG places the TI380C30 into slow-clock mode. The frequency of the reference
timer is in the range of 10 kHz – 100 kHz.
physical-layer interface (PHY)
The major blocks of the TI380C30 PHY include the receiver / equalizer, clock recovery PLL, wrap function,
phantom drive with wire-fault detector, and watchdog timer. Figure 2 is the block diagram illustrating these major
blocks, and the functionality of each block is described in the following sections.
WRAP
External
Equalizer
EQ +
EQ –
XTAL
8 MHz
XT1 XT2
S4 / 16
ATEST
FRAQ
NABL
RCV+
RCV–
Receiver
OSC
CKT
RCV
Data
Receiver
Clock
Recovery
FRAQ
XMT+
XMT–
PHOUTA
PHOUTB
PWRDN
Transmit
Phantom
Drive
Bias Gen
Watchdog
Timer (22 ms)
Error Rate
Test Port
PXTAL
RCVR
RCLK
OSC32
REDY
DRVR+
DRVR–
WFLT
RATER
NSRT
(internal)
IREF
TDI TDO TLCK TMS TRST
Figure 2. Functional Block Diagram of the PHY
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