TI380C30 Datasheet, PDF (59/78 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30
INTEGRATED TOKEN-RING
COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE
SPWS016A – NOVEMBER 1994 – REVISED JULY 1995
80x8x-mode bus-arbitration timing, SIF returns control
25-MHz
NO.
OPERATION
MIN MAX
220†
Delay time, SBCLK low in I1 cycle to SADH0 – SADH7, SADL0 – SADL7, SPL, SPH,
SRD, and SWR in the high-impedance state
35
223b† Delay time, SBCLK low in I1 cycle to SBHE in the high-impedance state
45
224b Delay time, SBCLK low in cycle I2 to SOWN high
0
20
224d Delay time, SBCLK low in cycle I2 to SDDIR high
27
230 Delay time, SBCLK high in cycle I1 to SHRQ low
20
240†
Setup time, SRD, SWR, and SBHE in the high-impedance state before SOWN no longer
low
0
† _{This specification has been characterized to meet stated value. It is not assured during manufacturing testing.}
33-MHz
OPERATION
MIN MAX
35
45
0
15
22
15
0
UNIT
ns
ns
ns
ns
ns
ns
SBCLK
SIF Master
T3
T4
Bus Exchange
I1
I2
User Master
(T1)
(T2)
SHLDA
SIF Outputs:
SHRQ ^‡
SRD, SWR
SBHE
SADH0 – SADH7,
SADL0 – SADL7,
SPH, SPL
SDDIR
SOWN ^§
230
220
Hi-Z
240
223b
SIF
Hi-Z
220
240
SIF
Hi-Z
Write
224d
Read
224b
‡ _{In 80x8x mode, the system interface deasserts SHRQ on the rising edge of SBCLK following the T4 state of the last system bus transfer it controls.}
In 68xxx mode, the system interface deasserts SBRQ on the rising edge of SBCLK in state T2 of the first system bus-transfer it controls.
§ _{While the system-interface DMA controls are active (i.e., SOWN is asserted), SCS is disabled.}
Figure 26. 80x8x-Mode Bus-Arbitration Timing, SIF Returns Control
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