TI380C30 Datasheet, PDF (60/78 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30
INTEGRATED TOKEN-RING
COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE
SPWS016A – NOVEMBER 1994 – REVISED JULY 1995
80x8x-mode bus-release timing
NO.
208a
Setup time, asynchronous input SBRLS low before SBCLK no longer high to assure
recognition
208b Hold time, asynchronous input SBRLS low after SBCLK low to assure recognition
208c Hold time, SBRLS low after SOWN high
25-MHz
OPERATION
MIN MAX
10
10
0
33-MHz
OPERATION
MIN MAX
10
10
0
UNIT
ns
ns
ns
SBCLK ^†
SBRLS ^‡
T(W or 2)
T3
T4
T1
T2
208a
208b
SOWN
208c
† _{Unless otherwise specified, for all signals specified as a maximum delay from the end of an SBCLK transition to the signal valid, the signal is}
also specified to hold its previous value (including high impedance) until the start of that SBCLK transition.
‡ _{The system interface ignores the assertion of SBRLS if it does not own the system bus. If it does own the bus, when it detects the assertion of}
SBRLS, it completes any internally started DMA cycle and relinquishes control of the bus. If no DMA transfer has started internally, the system
interface releases the bus before starting another.
Figure 27. 80x8x-Mode Bus-Release Timing
60
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