TI380C30 Datasheet, PDF (6/78 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30
INTEGRATED TOKEN-RING
COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE
SPWS016A – NOVEMBER 1994 – REVISED JULY 1995
Pin Functions (Continued)
PIN
NAME
NO.
I/O/E†
DESCRIPTION
MAL
Memory-address latch. MAL is a strobe signal for sampling the address at the start of the memory
cycle; it is used by SRAMs and EPROMs. The full 20-bit word address is valid on MAX0, MAXPH,
MAX2, MAXPL, MADH0 – MADH7, and MADL0 – MADL7. Three 8-bit transparent latches can be used
2
O
to retain a 20-bit static address throughout the cycle.
Rising edge = No signal latching
Falling edge = Allows the above address signals to be latched
MAX0
Local-memory extended-address bit. MAX0 drives AX0 at row-address time and A12 at
column-address and data-valid times for all cycles. MAX0 can be latched by MRAS. Driving A12 eases
interfacing to a burn-in address (BIA) ROM.
16
I/O
Memory Cycle
1Q
2Q
3Q
4Q
Signal
AX0
A12
A12
A12
MAX2
Local-memory extended-address bit. MAX2 drives AX2 at row-address time, which can be latched by
MRAS, and A14 at column-address and data-valid times for all cycles. Driving A14 eases interfacing
17
I/O
to a BIA ROM.
Memory Cycle
1Q
2Q
3Q
4Q
Signal
AX2
A14
A14
A14
MAXPH
Local-memory extended address and parity — high byte. For the first quarter of a memory cycle,
MAXPH carries the extended-address bit AX1; for the second quarter of a memory cycle, MAXPH
carries the extended-address bit AX0; and for the last half of the memory cycle, MAXPH carries the
35
I/O
parity bit for the high data byte.
Memory Cycle
1Q
2Q
3Q
4Q
Signal
AX1
AX0
Parity
Parity
MAXPL
Local-memory extended address and parity — low byte. For the first quarter of a memory cycle, MAXPL
carries the extended-address bit AX3; for the second quarter of a memory cycle, MAXPL carries
extended-address bit AX2; and for the last half of the memory cycle, MAXPL carries the parity bit for
39
I/O
the low data byte.
Memory Cycle
1Q
2Q
3Q
4Q
Signal
AX3
AX2
Parity
Parity
MBCLK1
MBCLK2
Local-bus clock 1 and local-bus clock 2. MBCLK1 and MBCLK2 are referenced for all local-bus
transfers. MBCLK2 lags MBCLK1 by a quarter of a cycle. MBCLK1 and MBCLK2 operate according
to:
173
174
O
MBCLK [1:2]
OSCIN
CLKDIV
8 MHz
64 MHz
H
8 MHz
32 MHz
L
12 MHz
48 MHz
L
MBEN
Buffer enable. MBEN enables the bidirectional buffer outputs on the MADH, MAXPH, MAXPL, and
MADL buses during the data phase. MBEN is used in conjunction with MDDIR, which selects the
24
O
buffer-output direction.
H = Buffer output disabled
L = Buffer output enabled
MBGR
37
I/O
Reserved; must be left unconnected
Burned-in address enable. MBIAEN is an output signal used to provide an output enable for the ROM
containing the adapter’s BIA.
MBIAEN
176
O
H = MBIAEN is driven high for any write accesses to the addresses between > 00.0000 and
> 00.000F, or any accesses (read/write) to any other address.
L = MBIAEN is driven low for any read from addresses between > 00.0000 and > 00.000F.
† _{I = input, O = output, E = provides external-component connection to the internal circuitry for tuning}
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