TI380C30 Datasheet, PDF (24/78 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30
INTEGRATED TOKEN-RING
COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE
SPWS016A – NOVEMBER 1994 – REVISED JULY 1995
SIF adapter-control register (SIFACL)
The SIFACL register allows the host processor to control and to some extent reconfigure the TI380C30 under
software control.
SIFACL Register
Bit # 0 1 2 3
4
5
TTT
EEE
S S S — SWHLDA SWDDIR
TTT
012
RRR
RP – 0
R –u
6
SWHRQ
R –0
7
PSDMAEN
RS – 0
8
9
10
ARESET CPHALT BOOT
RW – 0 RP – b RP – b
11
LBP
RW – 0
12
13
SINTEN PEN
RW – 1 RP – p
14
NSEL
OUT0
RP – 0
15
NSEL
OUT1
RP – 1
Legend:
R=
W=
P=
S=
–n =
b=
p=
u=
Read
Write
Write during ARESET = 1 only
Set only
Value after reset
Value on BTSTRP
Value on PRTYEN
Indeterminate
Bits 0 – 2: Value on TEST0 and TEST2 pins
These bits are read only and reflect the value on the corresponding device pins. This allows the
host S / W to determine speed configuration. If the network speed and type are software
configurable, these bits are used to determine which configurations are supported by the
network hardware.
TEST0 TEST1 TEST2 Description
L
NC
H
16-Mbps token ring
H
NC
H
4-Mbps token ring
X
X
L
Reserved
Bit 3:
Reserved. Read data is indeterminate.
Bit 4:
SWHLDA — Software-Hold Acknowledge
Allows the function of SHLDA / SBGR to be emulated from software control for pseudo-DMA
mode.
PSDMAEN
SWHLDA
SWHRQ
0^†
X
X
1^†
0
0
1^†
0
1
1^†
1
X
† _{The value on SHLDA / SBGR is ignored.}
RESULT
SWHLDA value in the SIFACL register cannot be set to a one.
No pseudo-DMA request pending
Indicates a pseudo-DMA request interrupt
Pseudo-DMA process in progress
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