TI380C30 Datasheet, PDF (17/78 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30
INTEGRATED TOKEN-RING
COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE
SPWS016A – NOVEMBER 1994 – REVISED JULY 1995
system interface (SIF) (continued)
When the TI380C30 enters the slow-clock mode, the clock that failed is replaced by a slow free-running clock,
and the device is placed into a low-power reset state. When the failed clock(s) return to valid operation, the
TI380C30 must be reinitialized.
For DMA with a 16-MHz clock, a continuous transfer rate of 64 Mbps ( 8 MBps) can be obtained. For DMA with
a 25-MHz clock, a continuous transfer rate of 96 Mbps (12 MBps) can be obtained. For DMA with a 33-MHz
clock, a continuous transfer rate of 128 Mbps ( 16MBps) can be obtained. For 8-bit and 16-bit pseudo-DMA,
the following data rates can be obtained:
LOCAL BUS SPEED
4 MHz
6 MHz
8-BIT PDMA
48 Mbps
72 Mbps
16-BIT PDMA
64 Mbps
96 Mbps
Since the main purpose of DIO is for downloading and initialization, the DIO transfer rate is not a significant
issue.
memory interface (MIF)
The MIF performs memory management to allow the TI380C30 to address 2 Mbytes in local memory. Hardware
in the MIF allows the TI380C30 to be directly connected to DRAMs without additional circuitry. This
glueless-DRAM connection includes the DRAM refresh controller. The MIF also handles all internal bus
arbitration between these blocks. When required, the MIF arbitrates for the external bus.
The MIF is responsible for the memory mapping of the CPU of a task. The memory map of DRAMs, EPROMs,
burned-in addresses (BIA), and external devices are appropriately addressed when required by the system
interface, protocol handler when required for a DMA transfer. The memory interface is capable of a 64-Mbps
continuous transfer rate when using a 4-MHz local bus (64-MHz device crystal) and a 96-Mbps continuous
transfer rate when using a 6-MHz local bus.
protocol handler (PH)
The PH performs the hardware-based real-time protocol functions for a token-ring LAN. Network type is
determined by TEST0 – TEST2. Token-ring network is determined by software and can be either 16 Mbps or
4 Mbps. These speeds are fixed by the software not by the hardware.
The PH converts the parallel-transmit data to serial-network data of the appropriate coding and converts the
received serial data to parallel data. The PH data-management state machines direct the
transmission/ reception of data to / from local memory through the MIF. The PH buffer-management state
machines automatically oversee this process, directly sending / receiving linked lists of frames without CPU
intervention.
The PH contains many state machines that provide the following features:
D Transmit and receive frames
D Capture tokens
D Provide token-priority controls
D Manage the TI380C30 buffer memory
D Provide frame-address recognition (group, specific, functional, and multicast)
D Provide internal parity protection
D Control and verify the physical-layer circuitry-interface signals
Integrity of the transmitted and received data is assured by cyclic-redundancy checks (CRC), detection of
network-data violations, and parity on internal data paths. All data paths and registers are optionally parity
protected to assure functional integrity.
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
17