TI380C30 Datasheet, PDF (68/78 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

User Master
SIF Inputs:
( T4)
SBCLK
SBGR
Bus Exchange
I1
I2
SIF Master
TX
T1
T2
208a
208b
SBERR,
SDTACK,
SBBSY
SIF Outputs:
230
230
SBRQ ^†
SAS, SLDS,
SUDS
SRNW
SADH0 –
SADH7,
SADL0 –
SADL7,
SPH, SPL
SDDIR
SOWN ^‡
208a
Input
208b
212
Hi-Z
224c
224a
241a
241
Output
241
Read
Write
SIF
Write
Read
† _{In 80x8x mode, the system interface deasserts SHRQ on the rising edge of SBCLK following the T4 state of the last system-bus transfer it controls. In 68xxx mode, the system}
interface deasserts SBRQ on the rising edge of SBCLK in state T2 of the first system-bus transfer it controls.
‡ _{While the system-interface DMA controls are active (i.e., SOWN is asserted), the SCS input is disabled.}
Figure 31. 68xxx-Mode Bus-Arbitration Timing, SIF Takes Control