TI380C30 Datasheet, PDF (13/78 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30
INTEGRATED TOKEN-RING
COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE
SPWS016A – NOVEMBER 1994 – REVISED JULY 1995
Pin Functions (Continued)
PIN
NAME
NO.
I/O/E†
DESCRIPTION
SWR is used for system-write strobe (see Note 7). SWR is an active-low write strobe that
is an input during DIO and an output during DMA.
Intel Mode _{H = Write cycle is not occurring.}
L = If DMA, data to be driven from SIF to host bus.
SWR / SLDS
77
I/O
If DIO, on the rising edge, the data is latched and written to the selected register.
SLDS is used for lower-data strobe (see Note 7). SLDS is an input during DIO and an
Motorola ^{output during DMA.}
Mode _{H = Not valid data on SADL0 – SADL7 lines}
L = Valid data on SADL0 – SADL7 lines
SXAL
System extended-address latch. SXAL provides the enable pulse used to externally latch the most
significant 16 bits of the 32-bit system address during DMA. SXAL is activated prior to the first cycle
79
O
of each block DMA transfer, and thereafter as necessary (whenever an increment of the DMA address
counter causes a carry out of the lower 16 bits). Systems that implement parity on addresses can use
SXAL to externally latch the parity bits (available on SPL and SPH) for the DMA address extension.
SYNCIN
12
I
Reserved. SYNCIN must be left unconnected (see Note 1).
S4 / 16
Speed switch. S4 / 16 specifies the token-ring data rate for the physical layer.
155
I
H = 4-Mbps data rate
L = 16-Mbps data rate
Intel Mode
S8 is used for system 8- /16-bit bus select. S8 selects the bus width used for
communications through the system interface. On the rising edge of SRESET, the
TI380C30 latches the DMA bus width; otherwise, the value on S8 dynamically selects
the DIO bus width.
S8 / SHALT
69
I
H = Selects 8-bit mode (see Note 1)
L = Selects 16-bit mode
Motorola
Mode
SHALT is used for system halt / bus error retry. If SHALT is asserted along with bus error
(SBERR), the adapter retries the last DMA cycle. This is the rerun operation as defined
in the 68xxx specification. The BERETRY counter is not decremented by SBERR when
SHALT is asserted (see Section 3.4.5.3 of the TMS380 Second-Generation Token-Ring
User’s Guide (SPWU005) for more information).
TCLK
TMS
TDI
TDO
7
I
8
165
I
I
Test ports used during the production test of the device. Should be left unconnected.
164
O
TEST0
TEST1
TEST2
Network select inputs. TEST0 – TEST2 are used to select the network speed and type to be used by
the TI380C30. These inputs should be changed only during adapter reset. Connect TEST2 to VDDL.
116
I
115
I
TEST0 TEST1 TEST2 DESCRIPTION
114
I
L
NC
H
16-Mbps token ring
H
NC
H
4-Mbps token ring
X
X
L
Reserved
TEST3
TEST4
TEST5
113
I
Test inputs. TEST3 – TEST5 should be left unconnected (see Note 1). Module-in-place test mode is
112
I
achieved by tying TEST3 and TEST4 to ground. In this mode, all TI380C30 outputs are in the
111
I
high-impedance state. Internal pullups on all TI380C30 inputs are disabled (except TEST3 – TEST5).
Test-port reset. TRST should be tied to ground for normal operation of the TI380C30.
TRST
9
I
H = Reserved
L = Test ports forced to an idle state
† _{I = input, O = output, E = provides external-component connection to the internal circuitry for tuning}
NOTES: 1. Pin has an internal pullup device to maintain a high-voltage level when left unconnected (no etch).
7. Pin should be tied to VDD with a 4.7-kΩ pullup resistor.
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