TI380C30 Datasheet, PDF (72/78 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

SBCLK
SAS
SUDS,
SLDS
SRNW
SXAL
SALE
SADL0 – SADH7,
SADH0 – SADL7,
SPL, SPH
SDTACK ^†‡
T4
TX§
TWAIT
V
T1
T2
T3
216
Low
222
211
233a
218
211a
217
217
218
216
223W
212
212
233
Extended Address
233
Address
219
Output Data
208a
T4
T1
209
216a
221
SDDIR
237W
208b
225W
225WH
SDBEN
† _{All VSS terminals should be routed to minimize inductance to system ground.}
‡ _{On a read cycle, the read strobe remains active until the internal sample of incoming data is completed. Input data can be removed when either the read strobe or SDBEN}
becomes no longer active.
§ _{In cycle-steal mode, state TX is present on every system bus transfer. In burst mode, state TX is present on the first bus transfer and whenever the increment of the DMA address}
register carries beyond the least significant 16 bits.
Figure 33. 68xxx-Mode DMA Write-Cycle Timing