TI380C30 Datasheet, PDF (5/78 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30
INTEGRATED TOKEN-RING
COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE
SPWS016A – NOVEMBER 1994 – REVISED JULY 1995
Pin Functions
PIN
NAME
NO.
I/O/E†
DESCRIPTION
ATEST
128
E
Analog test. Should be left unconnected.
BTSTRP
Bootstrap. The value on BTSTRP is loaded into the BOOT bit of the SIFACL register at reset (i.e., when
SRESET is asserted or the ARESET bit in the SIFACL register is set) to form a default value. BTSTRP
indicates whether chapters 0 and 31 of the memory map are RAM or ROM. If these chapters are RAM,
60
I
the TI380C30 is denied access to the local-memory bus until the CPHALT bit in the SIFACL register
is cleared.
H = Chapters 0 and 31 of local memory are RAM-based (see Note 1).
L = Chapters 0 and 31 of local memory are ROM-based.
Clock divider select (see Note 2)
CLKDIV
DRVR+
DRVR –
56
I
H = 64-MHz OSCIN for 4-MHz local bus
L = 32-MHz OSCIN for 4-MHz local bus or 48-MHz OSCIN for 6-MHz local bus
169
O
168
O
Differential-driver data outputs (reserved)
EQ +
EQ –
152
151
E
E
Equalization / gain points. Connections to allow frequency tuning of equalization circuit.
EXTINT0
EXTINT1
EXTINT2
EXTINT3
FRAQ
54
53
52
I/O
Reserved; must be pulled high (see Note 3)
51
Frequency-acquisition control.
122
O
H = Clock recovery PLL is initialized.
L = Normal operation
IREF
126
E
Internal reference. IREF allows the internal bias current of analog circuitry to be set via an external re-
sistor.
MACS
MADH0
MADH1
MADH2
MADH3
MADH4
MADH5
MADH6
MADH7
3
I
Reserved; must be tied low (see Note 4)
34
Local-memory address, data, and status bus — high byte. For the first quarter of the local-memory
33
cycle, these bus lines carry address bits AX4 and A0 to A6; for the second quarter, they carry status
32
bits; and for the third and fourth quarters, they carry data bits 0 to 7. The most significant bit is MADH0
31
28
I/O
and the least significant bit is MADH7.
27
Memory Cycle
26
1Q
2Q
3Q
4Q
25
Signal
AX4, A0 – A6 Status
D0 – D7
D0 – D7
MADL0
MADL1
MADL2
MADL3
MADL4
MADL5
MADL6
MADL7
50
Local-memory address, data, and status bus — low byte. For the first quarter of the local-memory
49
cycle, these bus lines carry address bits A7 to A14; for the second quarter, they carry address bits AX4
48
and A0 to A6; and for the third and fourth quarters, they carry data bits 8 to 15. The most significant
44
43
42
I/O
bit is MADL0 and the least significant bit is MADL7.
Memory Cycle
41
1Q
2Q
3Q
4Q
40
Signal
A7 – A14 AX4, A0 – A6 D8 – D15
D8 – D15
† _{I = input, O = output, E = provides external-component connection to the internal circuitry for tuning}
NOTES: 1. Pin has an internal pullup device to maintain a high-voltage level when left unconnected (no etch).
2. The TI380FPA and TMS380SRA are currently supported only with the 4-MHz local bus in either CLKDIV state. Expansion to support
the 6-MHz local bus is under development.
3. Each pin must be individually tied to VDD with a 1-kΩ pullup resistor.
4. Pin should be connected to ground.
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