TI380C30 Datasheet, PDF (71/78 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30
INTEGRATED TOKEN-RING
COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE
SPWS016A – NOVEMBER 1994 – REVISED JULY 1995
68xxx-mode DMA write-cycle timing
25-MHz OPERATION
33-MHz OPERATION
NO.
MIN
MAX
MIN
MAX
Setup time, asynchronous input SDTACK before
208a SBCLK no longer high to assure recognition on this
10
10
cycle
208b
Hold time, asynchronous input SDTACK after SBCLK
low to assure recognition on this cycle
10
10
209
Pulse duration, SAS, SUDS, and SLDS high
tc(SCK)+
tw(SCKL) – 18
tc(SCK)+
tw(SCKL) – 18
211
Delay time, SBCLK high in T2 cycle to SUDS and
SLDS active
25
25
211a
Delay time, output data valid to SUDS and SLDS no
longer high
tw(SCKL) – 15
tw(SCKL) – 15
212
Delay time, SBCLK low to address valid
20
20
216
Delay time, SBCLK high to SALE or SXAL high
20
20
216a
Hold time, SALE or SXAL low after SUDS and SAS
high
0
0
217
Delay time, SBCLK high to SXAL low in the TX cycle
or SALE low in the T1 cycle
0
25
0
25
218
Hold time, address valid after SALE, SXAL low
tw(SCKH) – 15 tc(SCK) / 2 – 4 tw(SCKH) – 15 tc(SCK) / 2 – 4
219
Delay time, SBCLK low in T2 cycle to output data and
parity valid
29
29
221
Hold time, output data, parity valid after SUDS and
SLDS high
tc(SCK) – 12
tc(SCK) – 12
222
Delay time, SBCLK high to SAS low
20
15
223W
Delay time, SBCLK low to SUDS, SLDS, and SAS
high
0
16
0
11
225W Delay time, SBCLK high in T4 cycle to SDBEN high
16
11
225WH Hold time, SDBEN low after SUDS and SLDS high
233
Setup time, address valid before SALE or SXAL no
longer high
tc(SCK) / 2 – 7
10
tc(SCK) / 2 – 7
10
233a Setup time, address valid before SAS no longer high tw(SCKL) – 15
tw(SCKL) – 15
237W Delay time, SBCLK high in T1 cycle to SDBEN low
16
11
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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