TI380C30 Datasheet, PDF (20/78 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30
INTEGRATED TOKEN-RING
COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE
SPWS016A – NOVEMBER 1994 – REVISED JULY 1995
receiver-clock recovery (continued)
RCV Data
PLL1
f3dB ≅ _{680 KHz}
PLL2
f3dB ≅ _{162 KHz}
RCLK
RCVR
NOTE A: f3dB = 3dB bandwidth of PLL
Figure 4. Dual PLL Arrangement
PLL1 represents the algorithm to recover data from the incoming stream detected by the receiver. It has a
relatively high bandwidth to provide good jitter tolerance. Data and embedded-clock-phase information are fed
as digital values to PLL2 that generates the extracted clock (RCLK) for the commprocessor. The recovered data
is sent to the commprocessor as the RCVR signal synchronously with RCLK. In addition to sampling the RCVR
signal, the commprocessor uses RCLK to retransmit data in most cases. The lower bandwidth of PLL2 greatly
reduces the rate of accumulation of data-correlated phase jitter in a token-ring network and provides very good
accumulated-phase-slope (APS) characteristics. In addition to RCLK, the token-ring reference clock (PXTAL)
and a fixed-frequency 32-MHz clock (OSC32) are also synthesized from the 8-MHz crystal reference.
line driver and wrap function
The line-drive function of the TI380C30 is performed by XMT+ / XMT–. Unlike the TMS38054, these pins are
low-impedance outputs and require external-series resistance to provide line termination. These pins provide
buffering of the differential signal from the PH on DRVR+/ DRVR– with action to control skew and asymmetry,
and with no retiming in the transmit path.
The wrap function is designed to provide a signal path for system self-test diagnostics. When the PH drives
WRAP low, the receiver inputs are ignored and the transmit signal is fed to the receiver input circuitry via a
multiplexer. In the internal wrap mode, WRAP can be checked by observing the signal amplitude at the
equalization pins, EQ + and EQ –. Equalization is active at this signal level, although the signal does not exhibit
the high-frequency attenuation effects for which equalization is intended to compensate. During wrap mode,
both XMT+ / XMT– are driven to a low state to prevent any dc current flowing in the isolation transformer.
phantom driver and wire-fault detection
The phantom-drive circuit under control of NSRT generates a dc voltage on both of the phantom-drive outputs,
PHOUTA and PHOUTB. In order to maintain the phantom drive, NSRT is toggled by the TI380C30 at least once
every 20 ms. A watchdog timer is included in the TI380C30 to remove the phantom drive if NSRT does not have
the required transitions.
The watchdog timer is normally not allowed to expire because it is being reinitialized at least every 20 ms. If there
is a problem in the TI380C30 or its microcode resulting in failure to toggle NSRT, the timer expires in a maximum
of 22 ms. If this happens, the phantom drive is deasserted and remains so until the next falling edge of NSRT.
The watchdog timer requires no external-timing components. When the phantom drive is deasserted, the
phantom-drive lines are actively pulled low, reaching a level of 1 V or less within 50 ms.
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