TI380C30 Datasheet, PDF (66/78 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30
INTEGRATED TOKEN-RING
COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE
SPWS016A – NOVEMBER 1994 – REVISED JULY 1995
SCS, SRSX,
SRS0, SRS1,
SBHE
Only SCS needs to be Inactive.
All others are don’t care.
267
SIACK
272a
286
SRNW
SLDS
273a
SDDIR
High
282R
283R
286
279
SDBEN
276
275
282a
SDTACK ^†
Hi-Z
255
Hi-Z
259
SADH0 – SADH7,
SADL0 – SADL7,
Hi-Z
SPH, SPL ^‡
260
Output Data Valid
261
261a
Hi-Z
† _{SDTACK is an active-low bus ready signal. It must be asserted before data output.}
‡ _{Internal logic drives SDTACK high and verifies that it has reached a valid-high level before making it a 3-state signal.}
Figure 30. 68xxx Interrupt-Acknowledge-Cycle Timing
66
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