TI380C30 Datasheet, PDF (21/78 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30
INTEGRATED TOKEN-RING
COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE
SPWS016A – NOVEMBER 1994 – REVISED JULY 1995
phantom driver and wire-fault detection (continued)
The dc voltage from PHOUTA and PHOUTB is superimposed on the transmit-signal pair to the trunk-coupling
unit (TCU) to request that the station be inserted into the ring. This is achieved by connecting the transmit-signal
pair to the center of the secondary winding of the transmit-isolation transformer. Since PHOUTA and PHOUTB
are connected to the media side of the isolation transformer, they require extensive protection against line
surges. A capacitor is connected between the two phantom lines to provide an ac path for the transmit signal,
while PHOUTA and PHOUTB independently drive the dc voltage on each of the transmit lines allowing for
independent wire-fault detection on each.
The phantom voltage is detected by the TCU, causing the external wrap path from the transmitter outputs back
to the receiver inputs to be broken and the ring to be broken. A signal connection is established from the ring
to the receiver inputs and from the transmitter outputs to the ring. The return current from the dc-phantom
voltage on the transmit pair is returned to the station via the receive pair. This provides some measure of
wire-fault detection on the receive lines. The phantom-drive outputs are current limited to prevent damage if
short circuited. They detect either an abnormally high or an abnormally low load current at either output
corresponding to a short or an open circuit in the ring or TCU wiring. Either type of fault results in the wire-fault
indicator output (WFLT) to be driven low. The logic state of WFLT is high when the phantom drive is not active.
frequency acquisition and REDY
Unlike its predecessors, the TMS3805x family, the data-recovery PLL of the TI380C30 physical layer does not
require constant frequency monitoring; neither is it necessary to recenter its frequency via the FRAQ control
line. When the commprocessor asserts FRAQ, it initiates a reset of the clock-recovery PLL. The REDY signal
is deasserted for the duration of this action and reasserted low when it is complete (a maximum of 3 µs later).
This low-going transition of REDY is required by the commprocessor following the setting of FRAQ high to
indicate to the PH that any frequency error that it could have detected has been corrected.
power-down control
The TI380C30 physical-layer interface can be disabled by the PWRDN signal. If PWRDN is taken low, all outputs
of the physical-layer interface are in the high-impedance state and all internal logic is powered down, bringing
power consumption to a very low level. Upon removing PWRDN, the device resets and initializes itself. This
process could take up to 2 ms and care should be taken to ensure that the system does not require stable clocks
during this period.
user-accessible hardware registers and TI380C30-internal pointers
The tables on the following pages show how to access internal data via pointers and how to address the registers
in the host interface. The SIFACL register, which directly controls device operation, is described in detail. The
adapter-internal pointers table is defined only after TI380C30 initialization and until the OPEN command is
issued. These pointers are defined by the TI380C30 software (microcode), and this table describes the release
2.x software.
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