TI380C30 Datasheet, PDF (34/78 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30
INTEGRATED TOKEN-RING
COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE
SPWS016A – NOVEMBER 1994 – REVISED JULY 1995
timing requirements over recommended range of supply voltage, t_c(XT1) = 125 ns (see Figure 8)
tc(XT1)
tw(OSC32H)
tw(OSC32L)
Cycle time of clock applied to XT1
Pulse duration, OSC32 high
Pulse duration, OSC32 low
tw(PXTALL) Pulse duration, PXTAL low
tw(PXTALH) Pulse duration, PXTAL high
tw(RCLKL) Pulse duration, RCLK low
tw(RCLKH) Pulse duration, RCLK high
tsu(RCVR)
th(RCVR)
Setup time, RCVR valid to RCLK rising edge
Hold time, RCVR valid after RCLK rising edge
tw(PXTALH)
TEST CONDITIONS
16-Mbps mode
4-Mbps mode
16-Mbps mode
4-Mbps mode
16-Mbps mode
4-Mbps mode
16-Mbps mode
4-Mbps mode
16-Mbps mode
16-Mbps mode
tw(PXTALL)
PXTAL
MIN TYP MAX UNIT
125
ns
10
ns
12
ns
12
ns
46
ns
10
ns
46
ns
12
ns
46
ns
10
ns
46
ns
18
ns
1
ns
2V
0.8 V
OSC32
RCLK
RCVR
tw(OSC32H)
tw(OSC32L)
tw(RCLKH)
tw(RCLKL)
tsu(RCVR)
th(RCVR)
Figure 8. PXTAL, RCLK, and RCVR Timing
2V
0.8 V
2V
0.8 V
2V
0.8 V
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