TI380C30 Datasheet, PDF (44/78 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30
INTEGRATED TOKEN-RING
COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE
SPWS016A – NOVEMBER 1994 – REVISED JULY 1995
memory-bus timing: DRAM-refresh timing
t_M is the cycle time of one-eighth of a local-memory cycle (31.25 ns minimum for a 4-MHz local bus or
20.83 ns minimum for a 6-MHz local bus).
NO.
15
16
18
19
73a
73b
73c
73d
Setup time, row address on MADL0 – MADL7, MAXPH, and MAXPL before MRAS no longer high
Hold time, row address on MADL0 – MADL7, MAXPH, and MAXPL after MRAS no longer high
Pulse duration, MRAS low
Pulse duration, MRAS high
Setup time, MCAS low before MRAS no longer high
Hold time, MCAS low after MRAS low
Setup time, MREF high before MCAS no longer high
Hold time, MREF high after MCAS high
MIN
1.5tM – 11.5
tM – 6.5
4.5tM – 5
3.5tM – 5
1.5tM –11.5
4.5tM – 6.5
14
tM – 9
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
MADL0 – MADL7
Refresh
Address
16
15
18
MRAS
73a
73b
MCAS
73c
MREF
Address
19
73d
Figure 15. Memory-Bus Timing: DRAM-Refresh Cycle
XMATCH and XFAIL timing
t_M is the cycle time of one-eighth of a local-memory cycle (31.25 ns minimum for a 4-MHz local bus or
20.83 ns minimum for a 6-MHz local bus).
NO.
127 Delay time, status bit 7 high to XMATCH and XFAIL recognized
128 Pulse duration, XMATCH or XFAIL high
MIN MAX UNIT
7tM
ns
50
ns
MADH7
Status
Bit 7
127
128
XMATCH,
XFAIL
Figure 16. XMATCH and XFAIL Timing
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