TI380C30 Datasheet, PDF (12/78 Pages) Texas Instruments – INTEGRATED TOKEN-RING COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE

TI380C30
INTEGRATED TOKEN-RING
COMMPROCESSOR AND PHYSICAL-LAYER INTERFACE
SPWS016A – NOVEMBER 1994 – REVISED JULY 1995
Pin Functions (Continued)
PIN
NAME
NO.
I/O/E†
DESCRIPTION
SRD / SUDS
SRD is used for system-read strobe (see Note 7). SRD is the active-low strobe indicating
that a read cycle is performed on the system bus. SRD is an input during DIO and an
output during DMA.
Intel Mode
H = Read cycle is not occurring.
98
I/O
L = If DMA, host provides data to system bus.
If DIO, SIF provides data to system bus.
Motorola
Mode
SUDS is used for upper-data strobe (see Note 7). SUDS is the active-low upper-data
strobe. SUDS is an input during DIO and an output during DMA.
H = Not valid data on SADH0 – SADH7 lines
L = Valid data on SADH0 – SADH7 lines
Intel Mode
SRDY is used for system bus ready (see Note 7). SRDY indicates to the bus master that
a data transfer is complete. SRDY is asynchronous but during DMA and pseudo-DMA
cycles, it is internally synchronized to SBCLK. During DMA cycles, SRDY must be
asserted before the falling edge of SBCLK in state T2 in order to prevent a wait state.
SRDY is an output when the TI380C30 is selected for DIO; otherwise, it is an input.
SRDY / SDTACK ⁹⁷
H = System bus is not ready.
L = Data transfer is complete; system bus is ready.
I/O
SDTACK is used for system data-transfer acknowledge (see Note 7). The purpose of
SDTACK is to indicate to the bus master that a data transfer is complete. SDTACK is
internally synchronized to SBCLK. During DMA cycles, SDTACK must be asserted
Motorola before the falling edge of SBCLK in state T2 in order to prevent a wait state. SDTACK
Mode is an output when the TI380C30 is selected for DIO; otherwise, it is an input.
H = System bus is not ready.
L = Data transfer is complete; system bus is ready.
SRESET
System reset. SRESET is activated to place the TI380C30 into a known initial state. Hardware reset
puts most of the TI380C30 outputs into the high-impedance state and places all blocks into the reset
state. The Intel-mode DMA bus-width selection (S8) is latched on the rising edge of SRESET.
62
I
H
= No system reset
L
= System reset
Rising edge = Latch bus width for DMA operations (for Intel-mode applications)
Intel Mode
SRSX and SRS0 – SRS2 are used for system-register select. These inputs select the
word or byte to be transferred during a system DIO access. The most significant bit is
SRSX and the least significant bit is SRS2 (see Note 1).
MSb
Register selected = SRSX
SRS0
SRS1
LSb
SRS2 / SBERR
SRSX
SRS0
SRS1
65
64
I
63
SRSX, SRS0 and SRS1 are used for system-register select. These inputs select the
word or byte to be transferred during a system DIO access. The most significant bit is
SRSX and the least significant bit is SRS1 (see Note 1).
SRS2 / SBERR
70
MSb
LSb
Motorola Register selected = SRSX
SRS0
SRS1
Mode
SBERR is used for bus error. SBERR corresponds to the bus-error signal of the 68xxx
microprocessor. It is internally synchronized to SBCLK. SBERR is driven low during a
DMA cycle to indicate to the TI380C30 that the cycle must be terminated (see Section
3.4.5.3 of the TMS380 Second-Generation Token-Ring User’s Guide (SPWU005) for
more information).
† _{I = input, O = output, E = provides external-component connection to the internal circuitry for tuning}
NOTES: 1. Pin has an internal pullup device to maintain a high-voltage level when left unconnected (no etch).
7. Pin should be tied to VDD with a 4.7-kΩ pullup resistor.
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